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| enhanced flash type 8-bit mcu with eeprom ht66f30-1 HT68F30-1 revision: v1.10 date: ? an?a ?? 1 ?? ?01 ? ?an?a?? 1 ?? ?01?
rev. 1.10 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom table of contents eates cpu feat ?? es ......................................................................................................................... ? pe ? iphe ? al feat ?? es ................................................................................................................. 8 gene?al desc?iption ......................................................................................... 9 selection table ................................................................................................. 9 block diag?am ................................................................................................ 10 pin assignment ........... .................................................................................... 11 pin desc?iption .......... .................................................................................... 1? absol?te maxim?m ratings .......................................................................... 15 d.c. cha?acte?istics (ht66f?0-1) ................................................................. 15 a.c. cha?acte?istics (ht66f?0-1) ................................................................. 1? a/d conve?te? cha?acte?istics (ht66f?0-1) ................................................ 18 d.c. cha?acte?istics (ht68f?0-1) ................................................................. 18 a.c. cha?acte?istics (ht68f?0-1) ................................................................. ?0 compa?ato? elect?ical cha?acte?istics (ht66f?0-1/ht68f?0-1) ........... ..... ?1 powe? on reset elect?ical cha?acte?istics (ht66f?0-1/ht68f?0-1) ......... ?1 s?stem a?chitect??e ...................................................................................... ?? clocking and pipelining ......................................................................................................... ?? p ? og ? am co ? nte ? ................................................................................................................... ?? stack ..................................................................................................................................... ? 4 a ? ithmetic and logic unit C alu ........................................................................................... ? 4 flash p?og?am memo?? ................................................................................. ?5 st ?? ct ?? e ................................................................................................................................ ? 5 special vecto ? s ..................................................................................................................... ? 5 look- ? p table ............. ........................................................................................................... ? 5 table p ? og ? am example ........................................................................................................ ? 6 in ci ? c ? it p ? og ? amming ......................................................................................................... ?? ram data memo?? ......................................................................................... ?8 st ?? ct ?? e ................................................................................................................................ ? 8 special f?nction registe? desc?iption ........................................................ ?1 indi ? ect add ? essing registe ? s C iar0 ? iar1 ......................................................................... ? 1 memo ?? pointe ? s C mp0 ? mp1 .............................................................................................. ? 1 bank pointe ? C bp ................................................................................................................. ?? acc ? m ? lato ? C acc ............................................................................................................... ?? p ? og ? am co ? nte ? low registe ? C pcl .................................................................................. ?? look- ? p table registe ? s C tblp ? tbhp ? tblh ..................................................................... ?? stat ? s registe ? C status .................................................................................................... ?? rev. 1.10 ? ?an?a?? 1?? ?01? rev. 1.10 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom eeprom data memory ........... ....................................................................... 35 eeprom data memo ?? st ?? ct ?? e ........................................................................................ ? 5 eeprom registe ? s ............ .................................................................................................. ? 5 reading data f ? om the eeprom ......................................................................................... ? 6 w ? iting data to the eeprom ................................................................................................ ?? w ? ite p ? otection ..................................................................................................................... ?? eeprom inte ??? pt ............. ................................................................................................... ?? p ? og ? amming conside ? ation ................................................................................................. ?? p ? og ? amming examples ........................................................................................................ ? 8 oscillator ........................................................................................................ 39 oscillato ? ove ? view ............. .................................................................................................. ? 9 system clock confgurations ................................................................................................ ? 9 exte ? nal c ?? stal/ce ? amic oscillato ? C hxt ........................................................................... 40 exte ? nal rc oscillato ? C erc ............. .................................................................................. 41 inte ? nal rc oscillato ? C hirc ............. .................................................................................. 41 exte ? nal ?? . ? 68khz c ?? stal oscillato ? C lxt ............. ........................................................... 4 ? lxt oscillato ? low powe ? f ? nction ...................................................................................... 4 ? inte ? nal ?? khz oscillato ? C lirc ........................................................................................... 4 ? s ? pplementa ?? clocks .......................................................................................................... 4 ? operating modes and system clocks ......................................................... 44 s ? stem clocks ...................................................................................................................... 44 s ? stem ope ? ation modes ...................................................................................................... 46 cont ? ol registe ? .................................................................................................................... 4 ? fast wake- ? p ........................................................................................................................ 48 ope ? ating mode switching and wake- ? p .............................................................................. 50 normal mode to slow mode switching ........................................................................... 50 slow mode to normal mode switching ........................................................................... 5 ? ente ? ing the sleep0 mode .................................................................................................. 5 ? ente ? ing the sleep1 mode .................................................................................................. 5 ? ente ? ing the idle0 mode ...................................................................................................... 5 ? ente ? ing the idle1 mode ...................................................................................................... 5 ? standb ? c ??? ent conside ? ations ........................................................................................... 5 ? wake- ? p ................................................................................................................................ 54 p ? og ? amming conside ? ations ............. ................................................................................... 54 watchdog timer ........... .................................................................................. 55 watchdog time ? clock so ?? ce .............................................................................................. 55 watchdog time ? cont ? ol registe ? ............. ............................................................................ 55 watchdog time ? ope ? ation ................................................................................................... 56 reset and initialisation .................................................................................. 57 reset f ? nctions ............. ....................................................................................................... 5 ? reset initial conditions ......................................................................................................... 60 rev. 1.10 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 5 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom input/output ports ......................................................................................... 65 p ? ll-high resisto ? s ................................................................................................................ 65 po ? t a wake- ? p ............. ........................................................................................................ 66 i/o po ? t cont ? ol registe ? s ..................................................................................................... 66 pin- ? emapping f ? nctions ...................................................................................................... 6 ? pin- ? emapping registe ? s ....................................................................................................... 6 ? i/o pin st ?? ct ?? es .................................................................................................................. 68 p ? og ? amming conside ? ations ............. ................................................................................... 69 timer modules C tm .......... ............................................................................ 69 int ? od ? ction ........................................................................................................................... 69 tm ope ? ation ............. ........................................................................................................... ? 0 tm clock so ?? ce ............. ...................................................................................................... ? 0 tm inte ??? pts ......................................................................................................................... ? 0 tm exte ? nal pins ................................................................................................................... ? 0 tm inp ? t/o ? tp ? t pin cont ? ol registe ? s ............. .................................................................... ? 1 p ? og ? amming conside ? ations ............. ................................................................................... ?? compact type tm C ctm .............................................................................. 74 compact tm ope ? ation ......................................................................................................... ? 5 compact t ? pe tm registe ? desc ? iption ................................................................................ ? 5 compact t ? pe tm ope ? ating modes .................................................................................... ? 9 compa ? e match o ? tp ? t mode ............................................................................................... ? 9 time ? /co ? nte ? mode ............................................................................................................. 8 ? pwm o ? tp ? t mode ............. ................................................................................................... 8 ? enhanced type tm C etm ........... .................................................................. 85 enhanced tm ope ? ation ....................................................................................................... 85 enhanced t ? pe tm registe ? desc ? iption .............................................................................. 86 enhanced t ? pe tm ope ? ating modes ................................................................................... 9 ? compa ? e o ? tp ? t mode ............. ............................................................................................. 9 ? time ? /co ? nte ? mode ............................................................................................................. 9 ? pwm o ? tp ? t mode ............. ................................................................................................... 9 ? single p ? lse mode .............................................................................................................. 10 ? capt ?? e inp ? t mode ............................................................................................................ 105 analog to digital converter .......... .............................................................. 108 a/d ove ? view ............. ......................................................................................................... 108 a/d conve ? te ? registe ? desc ? iption .................................................................................... 108 a/d conve ? te ? data registe ? s C adrl ? adrh ................................................................... 109 a/d conve ? te ? cont ? ol registe ? s C adcr0 ? adcr1 ? acerl ............................................. 109 a/d ope ? ation ...................................................................................................................... 11 ? a/d inp ? t pins ............. ......................................................................................................... 11 ? s ? mma ?? of a/d conve ? sion steps ............. ......................................................................... 114 p ? og ? amming conside ? ations ............. .................................................................................. 115 a/d t ? ansfe ? f ? nction ............. ............................................................................................. 115 a/d p ? og ? amming example .................................................................................................. 116 rev. 1.10 4 ?an?a?? 1?? ?01? rev. 1.10 5 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom comparators ................................................................................................. 118 compa ? ato ? ope ? ation ......................................................................................................... 118 compa ? ato ? registe ? s .......................................................................................................... 118 compa ? ato ? inte ??? pt ........................................................................................................... 1 ? 1 p ? og ? amming conside ? ations ............. ................................................................................. 1 ? 1 serial interface module C sim ..................................................................... 121 spi inte ? face ....................................................................................................................... 1 ? 1 spi inte ? face ope ? ation ....................................................................................................... 1 ?? spi registe ? s ............. ......................................................................................................... 1 ?? spi comm ? nication ............................................................................................................ 1 ? 6 i ? c inte ? face ............ ............................................................................................................ 1 ? 8 i ? c inte ? face ope ? ation ........................................................................................................ 1 ? 8 i ? c registe ? s ....................................................................................................................... 1 ? 9 i ? c b ? s comm ? nication ...................................................................................................... 1 ?? i ? c b ? s sta ? t signal ............................................................................................................. 1 ? 4 slave add ? ess ..................................................................................................................... 1 ? 4 i ? c b ? s read/w ? ite signal .................................................................................................. 1 ? 5 i ? c b ? s slave add ? ess acknowledge signal ....................................................................... 1 ? 5 i ? c b ? s data and acknowledge signal ............ ................................................................... 1 ? 5 peripheral clock output ........... ................................................................... 137 pe ? iphe ? al clock ope ? ation ............. .................................................................................... 1 ?? interrupts ...................................................................................................... 138 inte ??? pt registe ? s ............................................................................................................... 1 ? 8 inte ??? pt ope ? ation .............................................................................................................. 146 exte ? nal inte ??? pt ............. .................................................................................................... 149 compa ? ato ? inte ??? pt ........................................................................................................... 149 m ? lti-f ? nction inte ??? pt ........................................................................................................ 149 a/d conve ? te ? inte ??? pt ....................................................................................................... 150 time base inte ??? pts ........................................................................................................... 150 se ? ial inte ? face mod ? le inte ??? pts ............. .......................................................................... 15 ? exte ? nal pe ? iphe ? al inte ??? pt ............. .................................................................................. 15 ? eeprom inte ??? pt ............. ................................................................................................. 15 ? lvd inte ??? pt ....................................................................................................................... 15 ? tm inte ??? pts ....................................................................................................................... 15 ? inte ??? pt wake- ? p f ? nction ................................................................................................. 15 ? p ? og ? amming conside ? ations ............. ................................................................................. 154 power down mode and wake-up ................................................................ 155 ente ? ing the idle o ? sleep mode ............. ........................................................................ 155 standb ? c ??? ent conside ? ations ......................................................................................... 155 wake- ? p .............................................................................................................................. 156 low voltage detector C lvd .......... ............................................................. 157 lvd registe ? ............. .......................................................................................................... 15 ? lvd ope ? ation ..................................................................................................................... 158 rev. 1.10 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom scom function for lcd .............................................................................. 159 lcd ope ? ation ............. ....................................................................................................... 159 lcd bias cont ? ol ................................................................................................................ 160 confguration options ................................................................................. 161 application circuits ........... .......................................................................... 163 instruction set .............................................................................................. 165 int ? od ? ction ......................................................................................................................... 165 inst ?? ction timing ................................................................................................................ 165 moving and t ? ansfe ?? ing data ............................................................................................. 165 a ? ithmetic ope ? ations .......................................................................................................... 165 logical and rotate ope ? ation ............................................................................................. 166 b ? anches and cont ? ol t ? ansfe ? ........................................................................................... 166 bit ope ? ations ..................................................................................................................... 166 table read ope ? ations ....................................................................................................... 166 othe ? ope ? ations ............. .................................................................................................... 166 instruction set summary .......... .................................................................. 167 table conventions ............................................................................................................... 16 ? instruction defnition ................................................................................... 169 package information ................................................................................... 178 16-pin dip ( ? 00mil) o ? tline dimensions ............. ................................................................ 1 ? 8 16-pin nsop (150mil) o ? tline dimensions ......................................................................... 181 16-pin ssop (150mil) o ? tline dimensions ......................................................................... 18 ? ? 0-pin dip ( ? 00mil) o ? tline dimensions ............. ................................................................ 18 ? ? 0-pin sop ( ? 00mil) o ? tline dimensions ........................................................................... 185 ? 0-pin ssop (150mil) o ? tline dimensions ......................................................................... 186 ? 4-pin skdip ( ? 00mil) o ? tline dimensions ............. ........................................................... 18 ? ? 4-pin sop ( ? 00mil) o ? tline dimensions ........................................................................... 190 ? 4-pin ssop(150mil) o ? tline dimensions .......................................................................... 191 reel dimensions ................................................................................................................. 19 ? ca ?? ie ? tape dimensions ..................................................................................................... 19 ? rev. 1.10 6 ?an?a?? 1?? ?01? rev. 1.10 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom features cpu features ? operating v oltage: f sys =8mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v f sys =20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? five oscillators: external crystal - hxt external 32.768khz crystal - lxt external rc - erc internal rc - hirc internal 32khz rc - lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 4-level subroutine nesting ? bit manipulation instruction rev. 1.10 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 9 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom peripheral features ? flash program memory: 2k16 ? ram data memory: 968 ? eeprom memory: 648 ? watchdog t imer function ? up to 22 bidirectional i/o lines ? software controlled 4-scom lines lcd driver with 1/2 bias ? dual pin-shared external interrupts ? multiple t imer module for time measure, input capture, compare match output, pwm output or single pulse output function ? serial interfaces module with dual spi and i 2 c interfaces ? dual comparator functions ? dual t ime-base functions for generation of fxed time interrupt signals ? 8-channel 12-bit resolution a/d converter C ht66f30-1 ? low voltage reset function ? low voltage detect function ? wide range of available package types ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? eeprom data memory can be re-programmed up to 1,000,000 times ? eeprom data memory data retention > 10 years rev. 1.10 8 ?an?a?? 1?? ?01? rev. 1.10 9 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom general description the ht66f30-1 and HT68F30-1 series are flash memory with 8-bit high performance risc architecture microcontrollers, designed for a wide range of applications. of fering users the convenience of flash memory mult i-programming features, these devices also include a wide range of functio ns and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter and dual comparator functions. multiple and extremely flexible t imer modules provide timing, pulse generation and pwm generation fu nctions. c ommunication wi th t he ou tside wor ld i s c atered fo r b y i ncluding fu lly integrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means o f e asy c ommunication wi th e xternal p eripheral h ardware. pr otective f eatures su ch a s a n internal w atchdog t imer, low v oltage reset and low v oltage detector coupled with excellent noise imm unity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , lxt , erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vices wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. selection table most features are common to all devices, the main feature distinguishing them are adc funcftion. the following table summarises the main features of each device. part no. v dd program memory data memory data eeprom i/o ext. interrupt a/d timer module spi/ i 2 c spi stack package ht68f ? 0-1 ? . ? v~5.5v ? k16 968 648 ?? ? --- 10-bit ctm1 10-bit etm1 4 16 dip/nsop/ssop ? 0 dip/sop/ssop ? 4 skdip/sop/ssop ht66f ? 0-1 ? . ? v~5.5v ? k16 968 648 ?? ? 1 ? - bitx8 10-bit ctm1 10-bit etm1 4 16 dip/nsop/ssop ? 0 dip/sop/ssop ? 4 skdip/sop/ssop rev. 1.10 10 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 11 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom block diagram ?? ? ? ?? -? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - ? ? ? ? - ? note: only the ht66f30-1 device has a/d function. rev. 1.10 10 ?an?a?? 1?? ?01? rev. 1.10 11 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom pin assignment ht66f30-1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the / sign can be used for higher priority. rev. 1.10 1 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom HT68F30-1 ? ? ? ? ? ? note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the / sign can be used for higher priority. rev. 1.10 1? ?an?a?? 1?? ?01? rev. 1.10 1 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom pin description the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. ht66f30-1 pin name function op i/t o/t pin-shared mapping pa0~pa ? po ? t a pawu papu st cmos pb0~pb5 po ? t b pbpu st cmos pc0~pc ? po ? t c pcpu st cmos an0~an ? adc inp ? t acerl an pa0~pa ? vref adc ? efe ? ence inp ? t adcr1 an pb5 c0- ? c1- compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0+ ? c1+ compa ? ato ? 0 ? 1 inp ? t an pa ?? pc ? c0x ? c1x compa ? ato ? 0 ? 1 o ? tp ? t cmos pa0 ? pa5 tck0 ? tck1 tm0 ? tm1 inp ? t st pa ?? pa4 tp0_0 ? tp0_1 tm0 i/o tmpc0 st cmos pa0 ? pc5 tp1a tm1 i/o tmpc0 st cmos pa1 tp1b_0 ? tp1b_1 tm1 i/o tmpc0 st cmos pc0 ? pc1 int0 ? int1 ext. inte ??? pt 0 ? 1 st pa ?? pa4 pint pe ? iphe ? al inte ??? pt prm0 st pc ? o ? pc4 pck pe ? iphe ? al clock o ? tp ? t prm0 cmos pc ? o ? pc5 sdi spi data inp ? t prm0 st pa6 o ? pc0 sdo spi data o ? tp ? t prm0 cmos pa5 o ? pc1 scs spi slave select prm0 st cmos pb5 o ? pc6 sck spi se ? ial clock prm0 st cmos pa ? o ? pc ? scl i ? c clock prm0 st nmos pa ? o ? pc ? sda i ? c data prm0 st nmos pa6 o ? pc0 scom0~scom ? scom0~scom ? scomc scom pc0 ? pc1 ? pc6 ? pc ? osc1 hxt/erc pin co hxt pb1 osc ? hxt pin co hxt pb ? xt1 lxt pin co lxt pb ? xt ? lxt pin co lxt pb4 res reset inp ? t co st pb0 vdd powe ? s ? ppl ? * pwr avdd adc powe ? s ? ppl ? * pwr vss g ? o ? nd ** pwr avss adc g ? o ? nd ** pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt t rigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator rev. 1.10 14 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 15 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom *: vdd is the device power supply while a vdd is the adc power supply . the a vdd pin is bonded together internally with vdd. **: vss is the device ground pin while a vss is the adc ground pin. the a vss pin is bonded together internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. HT68F30-1 pin name function op i/t o/t pin-shared mapping pa0~pa ? po ? t a pawu papu st cmos pb0~pb5 po ? t b pbpu st cmos pc0~pc ? po ? t c pcpu st cmos c0- ? c1- compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0+ ? c1+ compa ? ato ? 0 ? 1 inp ? t an pa ?? pc ? c0x ? c1x compa ? ato ? 0 ? 1 o ? tp ? t cmos pa0 ? pa5 tck0 ? tck1 tm0 ? tm1 inp ? t st pa ?? pa4 tp0_0 ? tp0_1 tm0 i/o tmpc0 st cmos pa0 ? pc5 tp1a tm1 i/o tmpc0 st cmos pa1 tp1b_0 ? tp1b_1 tm1 i/o tmpc0 st cmos pc0 ? pc1 int0 ? int1 ext. inte ??? pt 0 ? 1 st pa ?? pa4 pint pe ? iphe ? al inte ??? pt prm0 st pc ? o ? pc4 pck pe ? iphe ? al clock o ? tp ? t prm0 cmos pc ? o ? pc5 sdi spi data inp ? t prm0 st pa6 o ? pc0 sdo spi data o ? tp ? t prm0 cmos pa5 o ? pc1 scs spi slave select prm0 st cmos pb5 o ? pc6 sck spi se ? ial clock prm0 st cmos pa ? o ? pc ? scl i ? c clock prm0 st nmos pa ? o ? pc ? sda i ? c data prm0 st nmos pa6 o ? pc0 scom0~scom ? scom0~scom ? scomc scom pc0 ? pc1 ? pc6 ? pc ? osc1 hxt/erc pin co hxt pb1 osc ? hxt pin co hxt pb ? xt1 lxt pin co lxt pb ? xt ? lxt pin co lxt pb4 res reset inp ? t co st pb0 vdd powe ? s ? ppl ? pwr vss g ? o ? nd pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt t rigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. rev. 1.10 14 ?an?a?? 1?? ?01? rev. 1.10 15 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. ...................................................................................................................... -80ma i ol t otal .............. ....................................................................................................................... 80ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics (ht66f30-1) 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hxt ? erc ? hirc) f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? . ? 5.5 v f sys = ? 0mhz 4.5 5.5 v i dd1 ope ? ating c ??? ent ? no ? mal mode ? f sys =f h (hxt ? erc ? hirc) ? v no load ? f sys =f h =4mhz ? adc off ? wdt enable 0. ? 1.1 ma 5v 1.8 ? . ? ma ? v no load ? f sys =f h =8mhz ? adc off ? wdt enable 1.6 ? .4 ma 5v ? . ? 5.0 ma ? v no load ? f sys =f h =1 ? mhz ? adc off ? wdt enable ? . ? ? . ? ma 5v 5.0 ? .5 ma i dd ? ope ? ating c ??? ent ? no ? mal mode ? f sys =f h (hxt) 5v no load ? f sys =f h = ? 0mhz ? adc off ? wdt enable 6.0 9.0 ma i dd ? ope ? ating c ??? ent ? slow mode ? f sys =f l (lxt ? lirc) ? v no load ? f sys =f l ? adc off ? wdt enable 10 ? 0 5v ? 0 50 i idle0 idle0 mode standb ? c ??? ent (lxt o ? lirc on) ? v no load ? adc off ? wdt enable 1.5 ? .0 5v ? .0 6.0 i idle1 idle1 mode standb ? c ??? ent (hxt ? erc ? hirc) ? v no load ? adc off ? wdt enable ? f sys =1 ? mhz on 0.55 0.8 ? ma 5v 1. ? 0 ? .00 ma i sleep0 sleep0 mode standb ? c ??? ent (lxt and lirc off) ? v no load ? adc off ? wdt disable 1 5v ? i sleep1 sleep1 mode standb ? c ??? ent (lxt o ? lirc on) ? v no load ? adc off ? wdt enable 1.5 ? .0 5v ? .5 5.0 v il1 inp ? t low voltage fo ? i/o po ? ts o ? inp ? t pins except res pin 0 0. ? v dd v v ih1 inp ? t high voltage fo ? i/o po ? ts o ? inp ? t pins except res pin 0. ? v dd v dd v v il ? inp ? t low voltage ( res) 0 0.4v dd v v ih ? inp ? t high voltage ( res) 0.9v dd v dd v rev. 1.10 16 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions v lvr lvr voltage level lvr enable ? ? .10v option -5% ? .10 +5% v lvr enable ? ? .55v option -5% ? .55 +5% v lvr enable ? ? .15v option -5% ? .15 +5% v lvr enable ? 4. ? 0v option -5% 4. ? 0 +5% v v lvd lvd voltage level lvden=1 ? v lvd = ? .0v -5% ? .00 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .4v -5% ? .40 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .0v -5% ? .00 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .6v -5% ? .60 +5% v lvden=1 ? v lvd =4.4v -5% 4.40 +5% v i lv additional powe ? cons ? mption if lvr and lvd is used lvr enable ? lvden=0 60 90 a lvr disable ? lvden=1 ? 5 115 a lvr enable ? lvden=1 90 1 ? 5 a v ol o ? tp ? t low voltage i/o po ? t ? v i ol =9ma 0. ? v 5v i ol = ? 0ma 0.5 v v oh o ? tp ? t high voltage i/o po ? t ? v i oh =- ? . ? ma ? . ? v 5v i oh =- ? .4ma 4.5 v r ph p ? ll-high resistance fo ? i/o po ? ts ? v ? 0 60 100 k 5v 10 ? 0 50 k i scom scom ope ? ating c ??? ent 5v scomc ? isel[1:0]=00 1 ? .5 ? 5.0 ?? .5 a scomc ? isel[1:0]=01 ? 5 50 65 a scomc ? isel[1:0]=10 ? 0 100 1 ? 0 a scomc ? isel[1:0]=11 140 ? 00 ? 60 a v scom v dd / ? voltage fo ? lcd com 5v no load 0.4 ? 5 0.500 0.5 ? 5 v dd v 1 ? 5 1. ? 5v refe ? enc e with b ? ffe ? voltage - ? % 1. ? 5 + ? % v i 1 ? 5 additional powe ? cons ? mption if 1. ? 5v refe ? ence with b ? ffe ? is ? sed ? 00 ? 00 a rev. 1.10 16 ?an?a?? 1?? ?01? rev. 1.10 1 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom a.c. characteristics (ht66f30-1) ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu ope ? ating clock ? . ? v~5.5v dc 8 mhz ? . ? v~5.5v dc 1 ? mhz 4.5v~5.5v dc ? 0 mhz f sys s ? stem clock (hxt) ? . ? v~5.5v 0.4 8 mhz ? . ? v~5.5v 0.4 1 ? mhz 4.5v~5.5v 0.4 ? 0 mhz f hirc s ? stem clock (hirc) ? v/5v ta=25?c - ? % 4 + ? % mhz ? v/5v ta=25?c - ? % 8 + ? % mhz 5v ta=25?c - ? % 1 ? + ? % mhz ? v/5v ta=0~70?c -5% 4 +5% mhz ? v/5v ta=0~70?c -4% 8 +4% mhz 5v ta=0~70?c -5% 1 ? + ? % mhz ? . ? v~ ? .6v ta=0~70?c - ? % 4 + ? % mhz ? .0v~5.5v ta=0~70?c -5% 4 +9% mhz ? . ? v~ ? .6v ta=0~70?c -6% 8 +4% mhz ? .0v~5.5v ta=0~70?c -4% 8 +9% mhz ? .0v~5.5v ta=0~70?c -6% 1 ? + ? % mhz ? . ? v~ ? .6v ta=-40?c~85?c -1 ? % 4 +8% mhz ? .0v~5.5v ta=-40?c~85?c -10% 4 +9% mhz ? . ? v~ ? .6v ta=-40?c~85?c -15% 8 +4% mhz ? .0v~5.5v ta=-40?c~85?c -8% 8 +9% mhz ? .0v~5.5v ta=-40?c~85?c -1 ? % 1 ? + ? % mhz f erc s ? stem clock (erc) 5v ta=25?c, r=120k* - ? % 8 + ? % mhz 5v ta=0~70?c, r=120k* -5% 8 +6% mhz 5v ta=-40?c~85?c, r=120k* - ? % 8 +9% mhz ? .0v~5.5v ta=-40?c~85?c, r=120k* -9% 8 +10% mhz ? . ? v~5.5v ta=-40?c~85?c, r=120k* -15% 8 +10% mhz f lxt s ? stem clock (lxt) ?? . ? 68 khz f lirc s ? stem clock (lirc) 5v ta=25?c -10% ?? +10% khz ? . ? v~5.5v ta=-40?c~85?c -50% ?? +60% khz f timer time ? inp ? t pin f ? eq ? enc ? 1 f sys t res exte ? nal reset low p ? lse width 1 s t int inte ??? pt p ? lse width 1 t sys t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to inte ??? pt ? 0 45 90 s t lvds lvdo stable time 15 s t bgs v bg t ?? n on stable time ? 00 s t eerd eeprom read time 45 90 s t eewr eeprom w ? ite time ? 4 ms t sst s ? stem sta ? t- ? p time ? pe ? iod (wake- ? p f ? om halt) f sys =hxt o ? lxt 10 ? 4 t sys f sys =erc o ? hirc 15~16 f sys =lirc osc 1~ ? 1rwh w sys i sys u i d h uhu ohudfh oo hfh h iuhhf d suhf uhu uhfpphh pdd h dffudf i h hudo + foodu iuhhf d hfso fdsdfu o eh fhfh ehhh d d ofdh d foh h hyfh d seoh rev. 1.10 18 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 19 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom a/d converter characteristics (ht66f30-1) ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition av dd a/d conve ? te ? ope ? ating voltage ? . ? 5.5 v v adi a/d conve ? te ? inp ? t voltage 0 v ref v v ref a/d conve ? te ? refe ? ence voltage ? av dd v dnl diffe ? ential non-linea ? it ? 5v t adck =1.0s 1 + ? lsb inl integ ? al non-linea ? it ? 5v t adck =1.0s ? +4 lsb i adc additional powe ? cons ? mption if a/d conve ? te ? is ? sed ? v no load (t adck =0.5s ) 0.90 1. ? 5 ma 5v no load (t adck =0.5s ) 1. ? 0 1.80 ma t adck a/d conve ? te ? clock pe ? iod 0.5 10 s t adc a/d conve ? sion time (incl ? de sample and hold time) 1 ? bit a/d conve ? te ? 16 t adck t ads a/d conve ? te ? sampling time 4 t adck t on ? st a/d conve ? te ? on-to-sta ? t time ? s d.c. characteristics (HT68F30-1) ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hxt ? erc ? hirc) f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? . ? 5.5 v f sys = ? 0mhz 4.5 5.5 v i dd1 ope ? ating c ??? ent ? no ? mal mode ? f sys =f h (hxt ? erc ? hirc) ? v no load ? f sys =f h =4mhz ? wdt enable 0. ? 1.1 ma 5v 1.8 ? . ? ma ? v no load ? f sys =f h =8mhz ? wdt enable 1.6 ? .4 ma 5v ? . ? 5.0 ma ? v no load ? f sys =f h =1 ? mhz ? wdt enable ? . ? ? . ? ma 5v 5.0 ? .5 ma i dd ? ope ? ating c ??? ent ? no ? mal mode ? f sys =f h (hxt) 5v no load ? f sys =f h = ? 0mhz ? wdt enable 6.0 9.0 ma i dd ? ope ? ating c ??? ent ? slow mode ? f sys =f l (lxt ? lirc) ? v no load ? f sys =f l ? wdt enable 10 ? 0 a 5v ? 0 50 a i idle0 idle0 mode standb ? c ??? ent (lxt o ? lirc on) ? v no load ? wdt enable 1.5 ? .0 ma 5v ? .0 6.0 ma i idle1 idle1 mode standb ? c ??? ent (hxt ? erc ? hirc) ? v no load ? wdt enable ? f sys =1 ? mhz on 0.55 0.8 ? ma 5v 1. ? 0 ? .00 ma i sleep0 sleep0 mode standb ? c ??? ent (lxt and lirc off) ? v no load ? wdt disable 1 a 5v ? a i sleep1 sleep1 mode standb ? c ??? ent (lxt o ? lirc on) ? v no load ? wdt enable 1.5 ? .0 a 5v ? .5 5.0 a v il1 inp ? t low voltage fo ? i/o po ? ts o ? inp ? t pins except res pin 0 0. ? v dd v v ih1 inp ? t high voltage fo ? i/o po ? ts o ? inp ? t pins except res pin 0. ? v dd v dd v v il ? inp ? t low voltage ( res) 0 0.4v dd v v ih ? inp ? t high voltage ( res) 0.9v dd v dd v rev. 1.10 18 ?an?a?? 1?? ?01? rev. 1.10 19 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions v lvr lvr voltage level lvr enable ? ? .10v option -5% ? .10 +5% v lvr enable ? ? .55v option -5% ? .55 +5% v lvr enable ? ? .15v option -5% ? .15 +5% v lvr enable ? 4. ? 0v option -5% 4. ? 0 +5% v v lvd lvd voltage level lvden=1 ? v lvd = ? .0v -5% ? .00 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .4v -5% ? .40 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .0v -5% ? .00 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .6v -5% ? .60 +5% v lvden=1 ? v lvd =4.4v -5% 4.40 +5% v i lv additional powe ? cons ? mption if lvr and lvd is ? sed lvr enable ? lvden=0 60 90 a lvr disable ? lvden=1 ? 5 115 a lvr enable ? lvden=1 90 1 ? 5 a v ol o ? tp ? t low voltage i/o po ? t ? v i ol =9ma 0. ? v 5v i ol = ? 0ma 0.5 v v oh o ? tp ? t high voltage i/o po ? t ? v i oh =- ? . ? ma ? . ? v 5v i oh =- ? .4ma 4.5 v r ph p ? ll-high resistance fo ? i/o po ? ts ? v ? 0 60 100 k 5v 10 ? 0 50 k i scom scom ope ? ating c ??? ent 5v scomc ? isel[1:0]=00 1 ? .5 ? 5.0 ?? .5 a scomc ? isel[1:0]=01 ? 5 50 65 a scomc ? isel[1:0]=10 ? 0 100 1 ? 0 a scomc ? isel[1:0]=11 140 ? 00 ? 60 a v scom v dd / ? voltage fo ? lcd com 5v no load 0.4 ? 5 0.500 0.5 ? 5 v dd rev. 1.10 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?1 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom a.c. characteristics (HT68F30-1) ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu ope ? ating clock ? . ? v~5.5v dc 8 mhz ? . ? v~5.5v dc 1 ? mhz 4.5v~5.5v dc ? 0 mhz f sys s ? stem clock (hxt) ? . ? v~5.5v 0.4 8 mhz ? . ? v~5.5v 0.4 1 ? mhz 4.5v~5.5v 0.4 ? 0 mhz f hirc s ? stem clock (hirc) ? v/5v ta=25?c - ? % 4 + ? % mhz ? v/5v ta=25?c - ? % 8 + ? % mhz 5v ta=25?c - ? % 1 ? + ? % mhz ? v/5v ta=0~70?c -5% 4 +5% mhz ? v/5v ta=0~70?c -4% 8 +4% mhz 5v ta=0~70?c -5% 1 ? + ? % mhz ? . ? v~ ? .6v ta=0~70?c - ? % 4 + ? % mhz ? .0v~5.5v ta=0~70?c -5% 4 +9% mhz ? . ? v~ ? .6v ta=0~70?c -6% 8 +4% mhz ? .0v~5.5v ta=0~70?c -4% 8 +9% mhz ? .0v~5.5v ta=0~70?c -6% 1 ? + ? % mhz ? . ? v~ ? .6v ta=-40?c~85?c -1 ? % 4 +8% mhz ? .0v~5.5v ta=-40?c~85?c -10% 4 +9% mhz ? . ? v~ ? .6v ta=-40?c~85?c -15% 8 +4% mhz ? .0v~5.5v ta=-40?c~85?c -8% 8 +9% mhz ? .0v~5.5v ta=-40?c~85?c -1 ? % 1 ? + ? % mhz f erc s ? stem clock (erc) 5v ta=25?c, r=120k* - ? % 8 + ? % mhz 5v ta=0~70?c, r=120k* -5% 8 +6% mhz 5v ta=-40?c~85?c, r=120k* - ? % 8 +9% mhz ? .0v~5.5v ta=-40?c~85?c, r=120k* -9% 8 +10% mhz ? . ? v~5.5v ta=-40?c~85?c, r=120k* -15% 8 +10% mhz f lxt s ? stem clock (lxt) ?? . ? 68 khz f lirc s ? stem clock (lirc) 5v ta=25?c -10% ?? +10% khz ? . ? v~5.5v ta=-40?c~85?c -50% ?? +60% khz f timer time ? inp ? t pin f ? eq ? enc ? 1 f sys t res exte ? nal reset low p ? lse width 1 s t int inte ??? pt p ? lse width 1 t sys t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to inte ??? pt ? 0 45 90 s t lvds lvdo stable time 15 s t bgs vbg t ?? n on stable time ? 00 s t eerd eeprom read time 45 90 s t eewr eeprom w ? ite time ? 4 ms t sst s ? stem sta ? t- ? p time ? pe ? iod (wake- ? p f ? om halt) f sys =hxt o ? lxt 10 ? 4 t sys f sys =erc o ? hirc 15~16 f sys =lirc osc 1~ ? 1rwh w sys i sys u i d h uhu ohudfh oo hfh h iuhhf d suhf uhu uhfpphh pdd h dffudf i h hudo + foodu iuhhf d hfso fdsdfu o eh fhfh ehhh d d ofdh d foh h hyfh d seoh rev. 1.10 ?0 ?an?a?? 1?? ?01? rev. 1.10 ? 1 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom comparator electrical characteristics (ht66f30-1/HT68F30-1) ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition v cmp compa ? ato ? ope ? ating voltage ? . ? 5.5 v i cmp compa ? ato ? ope ? ating c ??? ent ? v ?? 56 a 5v 1 ? 0 ? 00 a v cmpos compa ? ato ? inp ? t offset voltage -10 +10 mv v hys h ? ste ? esis width ? 0 40 60 mv v cm compa ? ato ? common mode voltage ? ange v ss v dd -1.4v v a ol compa ? ato ? open loop gain 60 80 db t pd compa ? ato ? ? esponse time ? v with 100mv ove ? d ? ive (note) ?? 0 560 ns 5v 1rwh 0hdvxuhg zlwk frpsdudwru rqh lqsxw slq dw 9 &0 9 dd oh h hu s s ud iup ss p u iup dd p power on reset electrical characteristics (ht66f30-1/HT68F30-1) ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition v por v dd sta ? t voltage to ens ?? e powe ? -on reset 100 mv rr vdd v dd rise rate to ens ?? e powe ? -on reset 0.0 ? 5 v/ms t por minim ? m time fo ? v dd to ? emain at v por to ens ?? e powe ? -on reset 1 ms rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/ o a nd a/ d c ontrol syst em wi th m aximum re liability a nd fe xibility. t his m akes t hese devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt , lxt , hirc, lirc or erc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented a t t he be ginning of t he t 1 c lock duri ng wh ich t ime a ne w i nstruction i s fe tched. t he remaining t2~t 4 clocks carry out the decodi ng and execution functi ons. in this way , one t1~t 4 clock cyc le form s one i nstruction cyc le. al though t he fet ching and exe cution of i nstructions t akes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. the exce ption to this are instructions where the content s of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ? ? ? ? ? ? ? ? system clocking and pipelining rev. 1.10 ?? ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is e xecuted e xcept f or i nstructions, su ch a s jmp o r call t hat d emand a j ump t o a non-consecutive pr ogram me mory a ddress. on ly t he l ower 8 b its, k nown a s t he pr ogram c ounter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register ht66f ? 0-1/ht68f ? 0-1 pc10~pc8 pcl ? ~pcl0 program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. rev. 1.10 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?5 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom stack this is a special part of the memory which is used to save the contents of the program counter only . the stack has four levels and is neit her part of the data nor part of the program space, and is neither readable nor writeable. the activate d level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a re turn i nstruction, re t or re ti, t he progra m count er i s re stored t o i ts pre vious va lue from t he stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti rev. 1.10 ?4 ?an?a?? 1?? ?01? rev. 1.10 ? 5 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for these devices series the program memory are flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, these flash device s of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 2k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. program memory structure look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the "t abrd [m]" or "t abrdl [m]" instructions, respectively . when the instruction is execut ed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table. rev. 1.10 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "700h" which refers to the start address of the last page within the 2k program memory of the ht6xf30-1. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "706h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "t abrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. rev. 1.10 ?6 ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address ; is referenced mov tblp, a ; to the last page or present page mov a, 07h ; initialise high table pointer mov tbhp, a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address 706h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address 705h transferred to ; tempreg2 and tblh in this example the data 1ah is ; transferred to tempreg1 and data 0fh to register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming the p rovision o f fl ash t ype pr ogram me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. t his enables product m anufacturers to e asily keep their manufactured products sup plied with the latest program releases without removal and re-insertion of the device. mcu programming pins function pa0 se ? ial data inp ? t/o ? tp ? t pa ? se ? ial clock res device reset vdd powe ? s ? ppl ? vss g ? o ? nd the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo ad ditional lines are required for the power supply and one line for the reset. the technical details regarding the incircuit programming of the devic e is beyond the scope of this document and will be supplied in supple mentary literature. during the programming process the res pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the p a0 and p a2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. rev. 1.10 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?9 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. programmer pin mcu pins res pb0 data pa0 clk pa ? programmer and mcu pins ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locatio ns within this area are read and write accessible under program control. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, w hich is only access ible in bank 1. sw itching betw een the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. data memory structure rev. 1.10 ?8 ?an?a?? 1?? ?01? rev. 1.10 ? 9 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ? ?? ? ?????????? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ht66f30-1 special purpose data memory rev. 1.10 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?1 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ? ?? ? ?????????? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? HT68F30-1 special purpose data memory rev. 1.10 ?0 ?an?a?? 1?? ?01? rev. 1.10 ? 1 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a,04h ; setup size of block m ov block,a mov a ,offset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0,a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc ram addresses. rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom bank pointer C bp the data memory is divided into two banks. selecting the data memory area is achieved using the bank pointer. bit 0 of the bank pointer is used to select data memory banks 0 or 1. the da ta me mory i s i nitialised t o ba nk 0 a fter a re set, e xcept for a w dt t ime-out re set i n t he power down mode, in which case, the data memory bank remains unaf fected. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register , care must be taken during programming. device bit 7 6 5 4 3 2 1 0 ht66f ? 0-1 ht68f ? 0-1 dmbp0 bp register list bp register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 dmbp0: select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. rev. 1.10 ?? ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. rev. 1.10 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?5 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x " x" ? nknown bit 7, 6 unimplemented, read as 0 bit 5 to: w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. rev. 1.10 ?4 ?an?a?? 1?? ?01? rev. 1.10 ? 5 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom eeprom data memory all devices contain an area of internal eeprom data memory . eeprom, which stands for electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 648 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into mem ory space and is therefore not directly addressable in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address ht66f ? 0-1/ht68f ? 0-1 648 00h~ ? fh eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register . the eec register however , being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list ? ht66f30-1/HT68F30-1 name bit 7 6 5 4 3 2 1 0 eea d5 d4 d ? d ? d1 d0 eed d ? d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por x x x x x x x ? nknown bit 7~6 unimplemented, read as 0 bit 5~0 data eeprom address data eeprom address bit 5~bit 0 rev. 1.10 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 undefned, read as 0 bit 3 wren: data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit rden: data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applic ation program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. rev. 1.10 ?6 ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom writing data to the eeprom to wr ite da ta t o t he e eprom, t he wr ite e nable bi t, w ren, i n t he e ec re gister m ust frst be se t high to enable the w rite function. the eep rom addres s of the data to be w ritten mus t then be placed in the eea register and the data placed in the eed register . if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fni shed c an be i mplemented e ither by pol ling t he w r bi t i n t he e ec re gister or by usi ng t he eeprom i nterrupt. w hen t he wr ite c ycle t erminates, t he w r b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write or read interrupt is generated when an eeprom write or read cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. howe ver a s t he e eprom i s c ontained wi thin a mul ti-function int errupt, t he a ssociated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request flag will both be set. if the global, eep rom and multi-function interrupts are enabled and the stack is not full, a jump to the a ssociated mul ti-function int errupt ve ctor wi ll t ake pl ace. w hen t he i nterrupt i s se rviced onl y the mult i-function int errupt fag wil l be automa tically reset , the ee prom int errupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. programming consideration care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. rev. 1.10 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?9 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom programming examples reading data from the eeprom C polling method mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; s etup b ank p ointer mov bp, a set iar1.1 ; s et r den b it, e nable r ead o perations set iar1.0 ; s tart r ead c ycle - s et r d b it back: sz iar1.0 ; c heck f or r ead c ycle e nd jmp back clr iar1 ; d isable e eprom r ead/write clr bp mov a, e ed ; m ove r ead d ata t o r egister mov read_data, a writing data from the eeprom C polling method mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, e eprom_data ; u ser d efned da ta mov eed, a mov a, 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; m p1 p oints t o e ec r egister mov a, 0 1h ; s etup b ank p ointer mov bp, a set iar1.3 ; s et w ren b it, e nable w rite o perations set iar1.2 ; s tart w rite c ycle - s et w r b it back: sz iar1.2 ; c heck f or w rite c ycle e nd jmp back clr iar1 ; d isable e eprom r ead/write clr bp rev. 1.10 ?8 ?an?a?? 1?? ?01? rev. 1.10 ? 9 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher perform ance but ca rry wi th i t t he disadva ntage of higher power requirem ents, whil e t he opposite is of course true for the lower frequency oscillators. w ith the capability of dynamically switching between fast and slow system clock, these devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte ? nal c ?? stal hxt 400khz~ ? 0mhz osc1/osc ? exte ? nal rc erc 8mhz osc1 inte ? nal high speed rc hirc 4 ? 8 ? 1 ? mhz exte ? nal low speed c ?? stal lxt ?? . ? 68khz xt1/xt ? inte ? nal low speed rc lirc ?? khz oscillator types system clock confgurations there are fve methods of generating the sys tem clock, three high speed oscillators and tw o low speed oscillators. the high speed oscillators are the external crystal/ceramic oscillator , external rc network oscillator and the inter nal 4mhz, 8mhz or 12mhz rc oscillator . the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators is chosen via c onfiguration opt ions. t he fre quency of t he sl ow spe ed or hi gh spe ed syst em c lock i s a lso determined using the hlclk bit and cks2~cks0 bits in the smod register . note that two oscillator selection s must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. rev. 1.10 40 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 41 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ? ? ? - ? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ?? system clock confgurations external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation. ? ? ? ? crystal/resonator oscillator C hxt rev. 1.10 40 ?an?a?? 1?? ?01? rev. 1.10 41 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom crystal oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note: 1. c1 and c ? val ? es a ? e fo ? g ? idance onl ? . crystal recommended capacitor values external rc oscillator C erc using the erc oscillator only requires that a resistor , with a value between 56k and 2.4m , is connected betw een o sc1 and v dd, and a capacitor is connected betw een o sc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation fre quency; t he e xternal c apacitor has no i nfuence ove r t he fre quency a nd i s c onnected for stability purposes only . device trimming during the manufacturing process and the inclusion of i nternal f requency c ompensation c ircuits a re u sed t o e nsure t hat t he i nfluence o f t he p ower supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 120k resistor connected and wi th a 5v vol tage powe r suppl y a nd t emperature of 25 ? c degrees, t he osc illator wi ll ha ve a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pb1, leaving pin pb2 free for use as a normal i/o pin. external rc oscillator erc internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as t hree fx ed f requencies o f e ither 4 mhz, 8 mhz o r 1 2mhz. de vice trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 ?c degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb1 and pb2 are free for use as normal i/o pins. rev. 1.10 4 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 4? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capa citor components connecte d to the 32.768khz crystal are necessary to provide oscillation. for a pplications wh ere p recise f requencies a re e ssential, t hese c omponents m ay b e r equired t o provide frequency compensation due to dif ferent crystal manufacturing tolerances. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. ? ? ? ?? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 ?? . ? 68khz 10pf 10pf note: 1. c1 and c ? val ? es a ? e fo ? g ? idance onl ? . ? . r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values rev. 1.10 4? ?an?a?? 1?? ?01? rev. 1.10 4 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 q ? ick sta ? t 1 low-powe ? after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into t he l ow-power m ode b y se tting t he l xtlp b it h igh. t he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it shou ld be no ted t hat, no m atter wha t c ondition t he l xtlp bi t i s se t t o, t he l xt osc illator wi ll always function normally , the only dif ference is that it will take more time to start up if in the low-power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz a t 5 v, r equiring n o e xternal c omponents f or i ts i mplementation. de vice t rimming d uring the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary clocks the l ow spe ed osc illators, i n a ddition t o pro viding a syst em c lock sour ce a re a lso use d t o pro vide a clock source to two other devices functions. these are the w atchdog t imer and the t ime base interrupts. rev. 1.10 44 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 45 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce ve rsa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the devices have many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the m ain sy stem c lock, c an c ome f rom e ither a h igh f requency, f h , o r l ow f requency, f l , so urce, and is s elected us ing the h lclk bit and ck s2~cks0 bits in the sm od regis ter. the high speed system clock can be sourced from either a hxt , erc or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from internal clock f l . if f l is selected then it can be sourced by either the lxt or lirc oscillators , selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the t ime base clock, f tbc . each of these internal clocks is sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. rev. 1.10 44 ?an?a?? 1?? ?01? rev. 1.10 45 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ?? ? ?? ? ?- ? ?? ?? ?? ?? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? ? ?? ? system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. together with f sys /4 it is also used as one of the clock sources for the w atchdog timer. the f tbc clock is used as a source for the t ime base interrupt functions and for the tms. rev. 1.10 46 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 4? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. operation mode description cpu f sys f sub f s f tbc normal mode on f h ~f h /64 on on on slow mode on f l on on on idle0 mode off off on on/off on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off ? normal mode as t he n ame sug gests t his i s o ne o f t he m ain o perating m odes wh ere t he m icrocontroller h as all of its functions operational and where the system clock is provided by one of the high speed os cillators. this mode operates allow ing the microcontroller to operate normally w ith a clock source will come from one of the high speed oscillators, either the hxt , erc or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high spe ed osc illator is use d, running the mi crocontroller at a divi ded clock ratio reduces the operating current. ? slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. ? sleep0 mode the sl eep0 mo de i s e ntered wh en a n hal t i nstruction i s e xecuted a nd wh en t he i dlen b it in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the w atchdog t imer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it wont enter the sleep0 mode. ? sleep1 mode the sleep1 mode is entered when an hal t instruction is executed and when the idlen bit in the smod registe r is low . in the sleep1 mode the cpu will be stopped. however , the f sub and f s clocks will continue to operate if the l vden is "1" or the w atchdog t imer function is enabled and if its clock source is chosen via confguration option to come from the f sub . ? idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the w dtc register is low. in the idle0 mode the system oscilla tor will be inhibit ed from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer, tms and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the w atchdog t imer clock, f s , will either be on or off depending upon the f s clock source. if the source is f sys /4 then the f s clock will be of f, and if the source comes from f sub then f s will be on. rev. 1.10 46 ?an?a?? 1?? ?01? rev. 1.10 4 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? idle1 mode the i dle1 mo de i s e ntered wh en a n hal t i nstruction i s e xecuted a nd wh en t he i dlen b it in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer, tms and sim. in the id le1 mode, the system oscillator will continue to run, and this system oscillator may be high s peed or low s peed sys tem oscillator . in the id le1 m ode the w atchdog t imer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on. control register a single register, smod, is used for overall control of the internal clocks within these devices. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 the system clock selection when hlclk is 0 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fast w ake-up control (only for hxt) 0: disable 1: enable this i s t he fa st w ake-up c ontrol b it wh ich d etermines i f t he f sub c lock so urce i s initially used after these devices wake up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. rev. 1.10 48 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 49 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom bit 2 hto: high speed system oscillator ready fag 0: not ready 1: ready this i s t he hi gh spe ed syst em osc illator re ady fl ag whi ch i ndicates whe n t he hi gh speed syst em osc illator i s st able. t his fa g i s c leared t o 0 by ha rdware wh en t hese devices are powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after devices power -on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycle s if the erc or hirc oscillator is used. bit 1 idlen: idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed these devices will enter the idle mode. in the idle1 mode the cpu will stop running but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson b it i s h igh. i f fsyson b it i s l ow, t he c pu a nd t he sy stem c lock wi ll a ll stop in idle0 mode. if the bit is low these devices will enter the sleep mode when a halt instruction is executed. bit 0 hlclk: system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. to minimise power consumption these devices can enter the sleep or idle0 mode, where the system clock source to these devices will be stopped. however when these devices are woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. t o ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator , to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast w ake-up function is f sub , the fast w ake-up function is only available in the sleep1 and idle0 modes. when these devices are woken up from the sleep0 mode, the fast wake-up function has no ef fect because the f sub clock is stopped. the fast w ake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc or h irc os cillator or lirc os cillator is us ed as the s ystem os cillator then it w ill take 15~16 clock cycle s of the erc or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases. rev. 1.10 48 ?an?a?? 1?? ?01? rev. 1.10 49 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10 ? 4 hxt c ? cles 10 ? 4 hxt c ? cles 1~ ? hxt c ? cles 1 10 ? 4 hxt c ? cles 1~ ? f sub c ? cles (s ? stem ?? ns with f sub frst fo ? 10 ? 4 hxt c ? cles and then switches ove ? to ?? n with the hxt clock) 1~ ? hxt c ? cles erc x 15~16 erc c ? cles 15~16 erc c ? cles 1~ ? erc c ? cles hirc x 15~16 hirc c ? cles 15~16 hirc c ? cles 1~ ? hirc c ? cles lirc x 1~ ? lirc c ? cles 1~ ? lirc c ? cles 1~ ? lirc c ? cles lxt x 10 ? 4 ltx c ? cles 10 ? 4 lxt c ? cles 1~ ? lxt c ? cles wake-up times note that if the w atchdog t imer is disabled, which means that the lxt and lirc are all both of f, then there will be no fast w ake-up function available when these devices wake-up from the sleep0 mode. ? ? ?? ? ? - ? ? ? - ? ? rev. 1.10 50 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 51 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom operating mode switching and wake-up these devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t i nstruction i s e xecuted, whe ther t hese de vices e nter t he idl e mode or t he sl eep mode is determ ined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h, to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when these devices move between the various operating modes. normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the sl ow mode is sourc ed from t he lxt or the lirc osci llators and the refore requi res these oscillators to be stable before full mode switching occurs. this is monitored using the l to bit in the smod register . rev. 1.10 50 ?an?a?? 1?? ?01? rev. 1.10 51 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? -?? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? - ?? ? rev. 1.10 5 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 5? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be se t t o 1 or hl clk bi t i s 0, but cks2~cks0 i s se t t o 010, 011, 100, 101, 110 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the ht o bit is checke d. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for these devices to enter the sleep0 mode and that is to execute the halt instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the sleep1 mode there is only one way for these devices to enter the sleep1 mode and that is to execute the halt instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt or l vd on. w hen t his i nstruction i s e xecuted unde r t he c onditions de scribed a bove, t he following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.10 5? ?an?a?? 1?? ?01? rev. 1.10 5 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom entering the idle0 mode there is only one way for these devices to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in wdtc register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction, but the t ime base clock and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for these devices to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in wdtc register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt wil l be cle ared and resume count ing if the wdt is enabled rega rdless of the wdt clock source which originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of these devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit de signer i f t he powe r c onsumption i s t o be m inimised. spe cial a ttention m ust be m ade t o the i /o p ins o n t hese d evices. al l h igh-impedance i nput p ins m ust b e c onnected t o e ither a fx ed high or low level as any foating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonded pins. these must eit her be set up as out puts or if setup as inputs must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. rev. 1.10 54 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 55 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if t he syst em i s woke n up by a n e xternal re set, t hese de vices wi ll e xperience a ful l syst em re set, however, i f t hese d evices a re wo ken u p b y a w dt o verflow, a w atchdog t imer r eset wi ll b e initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up these devices will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled o r wh en a st ack l evel b ecomes f ree. t he o ther si tuation i s wh ere t he r elated i nterrupt i s enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter . for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an of f state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if these devices are woken up from the sleep0 mode to the normal mode, the high speed system osc illator nee ds an sst peri od. t hese devi ces wi ll e xecute frst i nstruction aft er ht o is 1. at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator . the same situation occurs in the power -on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if these devices are woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1, the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt , tms and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/of f conditi on of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub . rev. 1.10 54 ?an?a?? 1?? ?01? rev. 1.10 55 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by confguration option: f sub or f sys /4. the f sub clock can be sourced from either the lx t or lirc oscillators , again chosen via a confguration option. the w atchdog timer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variat ions. the lxt oscillator is supplied by an external 32.768khz crystal. the other watchdog t imer clock source option is the f sys /4 clock. the w atchdog t imer clock source can originate from its own internal lirc oscillator , the lxt oscillator or f sys /4. it is divided by a value of 2 8 to 2 15 , using the ws2~ws0 bits in the wdtc register to obtain the required w atchdog t imer time-out period. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the w atchdog t imer. wdtc register bit ? 6 5 4 ? ? 1 0 name fsyson ws ? ws1 ws0 wdten ? wdten ? wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 1 0 1 0 bit 7 : f sys control in idle mode 0: disable 1: enable bit 6~4 : wdt time-out period selection 000: 256/f s 001: 512/f s 010: 1024/f s 011: 2048/f s 100: 4096/f s 101: 8192/f s 110: 16384/f s 111: 32768/f s these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. bit 3~0 : wdt software control 1010: disable other: enable rev. 1.10 56 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 5? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unkown loca tion, or enters an endless loop, these clear instruction s will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. some of the watchdog t imer options, s uch as enable/dis able, clock s ource s election and clear ins truction type are select ed using confguration options. in addition to a confguration option to enable/disable the watchdog t imer, there are also four bits, wdten3~wdten0, in the wdtc register to of fer an additional e nable/disable c ontrol o f t he w atchdog t imer. t o d isable t he w atchdog t imer, a s we ll as the confguration option being set to disable, the wdten3~wdten0 bits must also be set to a specifc value of " 1010". any other values for these bits will keep the w atchdog t imer enabled, irrespective of the confguration enable/disable setting. after power on these bits will have the value of 1010. if the w atchdog t imer is used it is recommended that they are set to a value of 0101 for maximum noise immunity . note that if the w atchdog t imer has been disabled, then any instruction relating to its operation will result in no operation. wdt confguration option wdten3~wdten0 bits wdt wdt enable xxxx enable wdt disable except 1010 enable wdt disable 1010 disable watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is an exte rnal hardware reset, which means a low level on the res pin, the second is using the w atchdog t imer software clear instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the w atchdog t imer, one of which must be chosen by confguration option. the frst option is to use the single "clr wdt" instruction while the second is to use the two commands "clr wdt1" and "clr wdt2". for the frst option, a s imple execution of " clr wd t" w ill clear the wd t w hile for the s econd option, both " clr wdt1" and "clr wdt2" must both be executed alternately to successfully clear the w atchdog timer. note that for this second option, if "clr wdt1" is used to clear the w atchdog t imer, successive executions of this instruction will have no ef fect, only the execution of a "clr wdt2" instruction will clear the w atchdog t imer. similarly after the "clr wdt2" instruction has been executed, only a successive "clr wdt1" instruction can clear the w atchdog t imer. the maximum time out period is when the 2 15 division ratio is selected. as an example, with a 32.768khz lxt oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum time out of 7.8ms for the 2 8 division ration. if the f sys /4 clock is used as the w atchdog t imer clock source, it should be noted that when the system enters the sleep or idle0 mode, then the instruction clock is stopped and the w atchdog t imer may lose its protecting purposes. for systems that operate in noisy environments, using the f sub clock source is strongly recommended. rev. 1.10 56 ?an?a?? 1?? ?01? rev. 1.10 5 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ?? ? ? ? ?? ? ?-? ? ?-? ? ? ? ? ?-? ? ? ? ? ? ? -? -? ?? ? ? ? ? ? ? ? ? ? ?? ? watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power -on reset, situations may arise where it is necessary to forcefully apply a reset c ondition wh en t he i s r unning. on e e xample o f t his i s wh ere a fter p ower h as b een a pplied and the is already running, the res line is forcefully pulled low . in such a case, known as a normal operation rese t, some of t he registers rem ain unchanged al lowing t he t o proc eed wi th norm al operation after the reset line is allowed to return high. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in dif ferent register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs afte r power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power -on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=100ms power-on reset timing chart rev. 1.10 58 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 59 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? res pin as t he re set pi n i s sha red wi th pb.0, t he re set func tion m ust be se lected usi ng a c onfguration option. although the microcontrolle r has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power -on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external r c n etwork i s c onnected t o t he res p in, wh ose a dditional t ime d elay wi ll e nsure t hat t he res pin remains low for an extend ed period to allow the power supply to stabilise. during this time dela y, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up t imer. for m ost a pplications a re sistor c onnected be tween vdd a nd t he res pi n a nd a c apacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applic ations that ope rate wit hin an environm ent where more noise is pre sent the enhanced reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. extern res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time=100ms res reset timing chart rev. 1.10 58 ?an?a?? 1?? ?01? rev. 1.10 59 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? low v oltage reset C lvr these microcontro llers contain a low voltage reset circuit in order to monitor the supply voltage of these devices, which are selected via a confguration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically res et the device internally . the l vr includes the follow ing s pecifications: for a valid l vr signal, a low volta ge, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not excee d t lvr , the l vr will ignore it and will not perform a reset function. one of a range of specifed voltage values for v lvr can be selected using confguration options. note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart ? watchdog t ime-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a hardware res pin reset except that the w atchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart ? watchdog t ime-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cle ared to 0 and the to fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart rev. 1.10 60 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 61 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset ? ? res o ? lvr ? eset d ?? ing normal o ? slow mode ope ? ation 1 ? wdt time-o ? t ? eset d ?? ing normal o ? slow mode ope ? ation 1 1 wdt time-o ? t ? eset d ?? ing idle o ? sleep mode ope ? ation ? stands fo ? ? nchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? am co ? nte ? reset to ze ? o inte ??? pts all inte ??? pts will be disabled wdt clea ? afte ? ? eset ? wdt begins co ? nting time ? /event co ? nte ? time ? co ? nte ? will be t ?? ned off inp ? t/o ? tp ? t po ? ts i/o po ? ts will be set ? p as inp ? ts ? and an0~an ? is as a/d inp ? t pin. stack pointe ? stack pointe ? will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes h ow e ach t ype o f re set a ffects e ach o f t he m icrocontroller i nternal re gisters. not e t hat where m ore t han one pa ckage t ype e xists t he t able wi ll re fect t he sit uation for t he l arger pa ckage type. rev. 1.10 60 ?an?a?? 1?? ?01? rev. 1.10 61 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1 register register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 -xxx xxxx -xxx xxxx -xxx xxxx - ??? ???? mp1 -xxx xxxx -xxx xxxx -xxx xxxx - ??? ???? bp ---- ---0 ---- ---0 ---- ---0 ---- --- ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp ---- -xxx ---- - ??? ---- - ??? ---- - ??? status --00 xxxx -- ?? ???? --1 ? ???? --11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc --00 -000 --00 -000 --00 -000 -- ?? - ??? integ ---- 0000 ---- 0000 ---- 0000 ---- ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 -000 0000 -000 0000 -000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? mfi0 --00 --00 --00 --00 --00 --00 -- ?? -- ?? mfi1 -000 -000 -000 -000 -000 -000 - ??? - ??? mfi ? 0000 0000 0000 0000 0000 0000 ???? ???? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu --00 0000 --00 0000 --00 0000 -- ?? ???? pb --11 1111 --11 1111 --11 1111 -- ?? ???? pbc --11 1111 --11 1111 --11 1111 -- ?? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? adrl(adref=0) xxxx ---- xxxx ---- xxxx ---- ???? ---- adrl(adref=1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adref=0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adref=1) ---- xxxx ---- xxxx ---- xxxx ---- ???? adcr0 0110 -000 0110 -000 0110 -000 ???? - ??? adcr1 00-0 -000 00-0 -000 00-0 -000 ?? - ? - ??? acerl 1111 1111 1111 1111 1111 1111 ???? ???? cp0c 1000 0--1 1000 0--1 1000 0--1 ???? ? -- ? cp1c 1000 0--1 1000 0--1 1000 0--1 ???? ? -- ? simc0 1110 000- 1110 000- 1110 000- ???? ??? - simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? sima/simc ? 0000 0000 0000 0000 0000 0000 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? rev. 1.10 6 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 6? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) tm0dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah ---- --00 ---- --00 ---- --00 ---- -- ?? eea --xx xxxx --xx xxxx --xx xxxx -- ?? ???? eed xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eec ---- 0000 ---- 0000 ---- 0000 ---- ???? tmpc0 1-01 --01 1-01 --01 1-01 --01 ? - ?? -- ?? prm0 ---- -000 ---- -000 ---- -000 ---- - ??? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1c ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah ---- --00 ---- --00 ---- --00 ---- -- ?? tm1bl 0000 0000 0000 0000 0000 0000 ???? ???? tm1bh ---- --00 ---- --00 ---- --00 ---- -- ?? scomc 0000 0000 0000 0000 0000 0000 ???? ???? note: - stands for not implement u stands for unchanged x stands for unknown rev. 1.10 6? ?an?a?? 1?? ?01? rev. 1.10 6 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom HT68F30-1 register register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 -xxx xxxx -xxx xxxx -xxx xxxx - ??? ???? mp1 -xxx xxxx -xxx xxxx -xxx xxxx - ??? ???? bp ---- ---0 ---- ---0 ---- ---0 ---- --- ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp ---- -xxx ---- - ??? ---- - ??? ---- - ??? status --00 xxxx -- ?? ???? --1 ? ???? --11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc --00 -000 --00 -000 --00 -000 -- ?? - ??? integ ---- 0000 ---- 0000 ---- 0000 ---- ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 -000 0000 -000 0000 -000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? mfi0 --00 --00 --00 --00 --00 --00 -- ?? -- ?? mfi1 -000 -000 -000 -000 -000 -000 - ??? - ??? mfi ? 0000 0000 0000 0000 0000 0000 ???? ???? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu --00 0000 --00 0000 --00 0000 -- ?? ???? pb --11 1111 --11 1111 --11 1111 -- ?? ???? pbc --11 1111 --11 1111 --11 1111 -- ?? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? cp0c 1000 0--1 1000 0--1 1000 0--1 ???? ? -- ? cp1c 1000 0--1 1000 0--1 1000 0--1 ???? ? -- ? simc0 1110 000- 1110 000- 1110 000- ???? ??? - simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? sima/simc ? 0000 0000 0000 0000 0000 0000 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah ---- --00 ---- --00 ---- --00 ---- -- ?? eea --xx xxxx --xx xxxx --xx xxxx -- ?? ???? eed xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eec ---- 0000 ---- 0000 ---- 0000 ---- ???? tmpc0 1-01 --01 1-01 --01 1-01 --01 ? - ?? -- ?? rev. 1.10 64 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 65 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) prm0 ---- -000 ---- -000 ---- -000 ---- - ??? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1c ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah ---- --00 ---- --00 ---- --00 ---- -- ?? tm1bl 0000 0000 0000 0000 0000 0000 ???? ???? tm1bh ---- --00 ---- --00 ---- --00 ---- -- ?? scomc 0000 0000 0000 0000 0000 0000 ???? ???? note: - stands for not implement u stands for unchanged x stands for unknown rev. 1.10 64 ?an?a?? 1?? ?01? rev. 1.10 65 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. these devices provide bidirectional input/output lines labeled with port names p a~pc these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list ? ht66f30-1/HT68F30-1 register name bit 7 6 5 4 3 2 1 0 pawu d ? d6 d5 d4 d ? d ? d1 d0 papu d ? d6 d5 d4 d ? d ? d1 d0 pa d ? d6 d5 d4 d ? d ? d1 d0 pac d ? d6 d5 d4 d ? d ? d1 d0 pbpu d5 d4 d ? d ? d1 d0 pb d5 d4 d ? d ? d1 d0 pbc d5 d4 d ? d ? d1 d0 pcpu d ? d6 d5 d4 d ? d ? d1 d0 pc d ? d6 d5 d4 d ? d ? d1 d0 pcc d ? d6 d5 d4 d ? d ? d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using registers, namely p apu~pcpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pbpu register bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 rev. 1.10 66 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 6? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom pcpu register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu: port a bit 7~bit 0 w ake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac~pcc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc register bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 rev. 1.10 66 ?an?a?? 1?? ?01? rev. 1.10 6 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom pcc register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port bit 7~bit 0 input/output control 0: output 1: input pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established whe re m ore t han one pi n func tion i s se lected si multaneously. addi tionally t here i s a prm0 register to establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the devices include a prm0 register which can select the functions of certain pins. pin-remapping register list register name bit 7 6 5 4 3 2 1 0 prm0 pcprm simps0 pckps prm0 register bit 7 6 5 4 3 2 1 0 name pcprm simps0 pckps r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2 pcprm: pc1~pc0 pin-shared function pin remapping control 0: no change 1: tp1b_0 on pc0 change to pa6, tp1b_1 on pc1 change to pa7 if simps0=1 bit 1 simps0: sim pin remapping control 0: sdo on pa5; sdi/sda on pa6; sck/scl on pa7; scs on pb5 1: sdo on pc1; sdi/sda on pc0; sck/scl on pc7; scs on pc6 bit 0 pckps: pck and pint pin remapping control 0: pck on pc2; pint on pc3 1: pck on pc5; pint on pc4 rev. 1.10 68 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 69 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. ??? ? ? ? ?? generic input/output structure ? ? ? ? ? ? - ? ? ? ? ? ? ? ? - a/d input/output structure rev. 1.10 68 ?an?a?? 1?? ?01? rev. 1.10 69 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pcc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pc, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming i ndividual b its i n t he p ort c ontrol re gister u sing t he set [m ].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. t o implement time related functions each device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either multiple interrupts. the addit ion of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and enhanced tm sections. introduction the devices conta in two tms having a reference name of tm0 and tm1. each individual tm can be categorised as a certain type, namely compact t ype tm or enhanced t ype tm. although similar in nature, the dif ferent tm types vary in their feature complexity . the common features to all of the compact and enhanced tms will be described in this section. the detailed operation regarding each of the tm types will be described in separate sections. the main featu res and dif ferences between the two types of tms are summarised in the accompanying table. function ctm etm time ? /co ? nte ? i/p capt ?? e compa ? e match o ? tp ? t pwm channels 1 ? single p ? lse o ? tp ? t ? pwm alignment edge edge & cent ? e pwm adj ? stment pe ? iod & d ? t ? d ? t ? o ? pe ? iod d ? t ? o ? pe ? iod tm function summary rev. 1.10 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?1 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom each device conta ins a single compact t ype and single enhanced t ype tm which are shown in the table together with their individual reference name, tm0 and tm1. device tm0 tm1 ht66f ? 0-1/ht68f ? 0-1 10-bit ctm 10-bit etm tm name/type reference tm operation the d ifferent t ypes o f t m o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations t o pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f l clock source or the external tckn pin. note that setting these bits to the value 101 will select an undefned clock input, in ef fect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact type tm has two internal interrupts, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p c ompare m atch funct ions, i t c onsequently ha s t hree i nternal i nterrupts. w hen a t m interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the p wm output w aveform. a s the tm output pins are pin-s hared w ith other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and devices are dif ferent, the details are provided in the accompanying table. rev. 1.10 ?0 ?an?a?? 1?? ?01? rev. 1.10 ? 1 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom all tm output pin names have a _n suffx. pin names that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm registers ht66f ? 0-1/ht68f ? 0-1 tp0_0 ? tp0_1 tp1a ? tp1b_0 ? tp1b_1 tmpc0 tm output pins tm input/output pin control registers selecting to have a tm input/outpu t or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 7 6 5 4 3 2 1 0 tmpc0 ht66f ? 0-1 ht68f ? 0-1 t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 tm input/output pin control registers list ht66f30-1/HT68F30-1 tm0 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input. rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 tm1 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input. rev. 1.10 ?? ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom tmpc0 register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w por 1 0 1 0 1 bit 7 t1acp0: tp1a pin control 0: disable 1: enable bit 6 unimplemented, read as "0" bit 5 t1bcp1: tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0: tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1 t0cp1: tp0_1 pin control 0: disable 1: enable bit 0 t0cp0: tp0_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these registe r pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related l ow b yte o nly t akes p lace wh en a wr ite o r r ead o peration t o i ts c orresponding h igh b yte i s executed. data b?s 8- bit b?ffe? tmxdh tmxdl tmxbh tmxbl tmxah tmxal tm co?nte? registe? ( read onl? ) tm ccra registe? ( read / w?ite ) tm ccrb registe? ( read / w?ite ) rev. 1.10 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?5 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom the following steps show the read and write procedures: ? writing data to ccrb or ccra ? step 1. w rite data to low byte tmxal or tmxbl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah or tmxbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl C this step reads data from the 8-bit buffer. compact type tm C ctm although the simplest form of the two t m types, the compact t m type still contains three operating modes, wh ich a re c ompare ma tch ou tput, t imer/event c ounter a nd pw m ou tput m odes. t he compact t m c an a lso be c ontrolled wi th a n e xternal i nput pi n a nd c an dri ve t wo e xternal out put pins. these two external output pins can be the same signal or the inverse signal. ctm name tm no. tm input pin tm output pin ht66f ? 0-1/ht68f ? 0-1 10-bit ctm 0 tck0 tp0_0 ? tp0_1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? compact type tm block diagram (n=0) rev. 1.10 ?4 ?an?a?? 1?? ?01? rev. 1.10 ? 5 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changi ng the value of the 10-bit count er using the appl ication program , is to clear the counter by changing the t0on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operat ion of t he compa ct tm i s c ontrolled usi ng si x regi sters. a rea d only regi ster pai r exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm0c0 t0pau t0ck ? t0ck1 t0ck0 t0on t0rp ? t0rp1 t0rp0 tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0dl d ? d6 d5 d4 d ? d ? d1 d0 tm0dh d9 d8 tm0al d ? d6 d5 d4 d ? d ? d1 d0 tm0ah d9 d8 compact tm register list tm0dl register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0dl: tm0 counter low byte register bit 7~bit 0 tm0 10-bit counter bit 7~bit 0 tm0dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm0dh: tm0 counter high byte register bit 1~bit 0 tm0 10-bit counter bit 9~bit 8 rev. 1.10 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom tm0al register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0al: tm0 ccra low byte register bit 7~bit 0 tm0 10-bit ccra bit 7~bit 0 tm0ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm0ah: tm0 ccra high byte register bit 1~bit 0 tm0 10-bit ccra bit 9~bit 8 tm0c0 register bit 7 6 5 4 3 2 1 0 name t0pau t0ck ? t0ck1 t0ck0 t0on t0rp ? t0rp1 t0rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t0pau: tm0 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t0ck2~t0ck0: select tm0 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: undefned 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm0. selecting the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t0on: tm0 counter on/off control 0: off 1: on rev. 1.10 ?6 ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom this bit controls the overall on/of f function of the tm0. setting the bit high enables the counter to run, clearing the bit disables the tm0. clearing this bit to zero will stop the counter from counting and turn of f the tm0 which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm0 is in the compare match output mode then the tm0 output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high. bit 2~0 t0rp2~t0rp0: tm0 ccrp 3-bit register, compared with the tm0 counter bit 9~bit 7 comparator p match period 000: 1024 tm0 clocks 001: 128 tm0 clocks 010: 256 tm0 clocks 011: 384 tm0 clocks 100: 512 tm0 clocks 101: 640 tm0 clocks 110: 768 tm0 clocks 111: 896 tm0 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 0cclr bi t i s se t t o zero. set ting t he t 0cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tm0c1 register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t 0 m1~t 0 m0: select tm 0 operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t0m1 and t0m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t0io1~t0io0: select tp0_0, tp0_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused rev. 1.10 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?9 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom these two bits are used to determine how the tm 0 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm 0 is running. in the compare match output mode, the t 0 io1 and t 0 io0 bits determine how the tm 0 output pin changes state when a compare match occurs from the comparator a. the t m 0 out put pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pre sent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm0 output pin should be setup using the t 0 oc bit in the tm 0 c1 register . note that the output level requested by the t 0 io1 and t 0 io0 bits must be dif ferent from the initial value setup using the t0oc bit otherwise no change will occur on the tm 0 output pin when a compare match occurs. after the tm 0 output pin changes state it can be reset to its initial level by changing the level of the t 0 on bit from low to high. in t he pw m mo de, t he t 0 io1 a nd t 0 io0 b its d etermine h ow t he t m o utput p in changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the v alues of t he t 0 io1 a nd t 0 io0 bi ts o nly a fter t he t m0 ha s be en swi tched of f. unpredictable pwm outputs will occur if the t 0 io1 and t 0 io0 bits are changed when the tm is running. bit 3 t0oc: tp 0 _0, tp 0 _1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm 0 output pin. its operation depends upon whether tm 0 is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm 0 is in the t imer/counter mode. in the compare match output mode i t de termines t he l ogic l evel of he t m0 ou tput pi n be fore a c ompare match oc curs. in t he pwm mode i t det ermines i f t he pwm si gnal i s a ctive hi gh or active low. bit 2 t0pol: tp0_0, tp0_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0_0 or tp0_1 output pin. when the bit is set high the tm0 output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm0 is in the t imer/counter mode. bit 1 t0dpx: tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr: select tm0 counter clear condition 0: tm0 comparator p match 1: tm0 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact t m0 c ontains t wo c omparators, c omparator a a nd c omparator p , e ither of which can be selected to clear the internal counter . w ith the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm mode. rev. 1.10 ?8 ?an?a?? 1?? ?01? rev. 1.10 ? 9 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t 0m1 a nd t 0m0 bits in the tm0c1 register. compare match output mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t0cclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow . here both t0af and t0pf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the t0cclr bit in the tm0c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t0af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t0cclr is high no t0pf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the t0af interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a t0af interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t 0pf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t0io1 and t0io0 bits in the tm0c1 register . the tm output pin can be selected using the t0io1 and t0io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t0on bit changes from low to high, is setup using the t0oc bit. note that if the t0io1 and t0io0 bits are zero then no pin change will take place. rev. 1.10 80 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 81 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e 0x? ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin time ccrp =0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed b? ccrp val?e pa?se res?me stop co?nte? resta?t tncclr = 0 ; tnm [1:0 ] = 00 o?tp?t pin set to initial level low if tnoc =0 o?tp?t toggle with tnaf flag note tnio [1:0 ] = 10 active high o?tp?t select he?e tnio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected b? tnaf flag . remains high ?ntil ?eset b? tnon bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnpol is high compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=0 rev. 1.10 80 ?an?a?? 1?? ?01? rev. 1.10 81 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed b? ccra val?e pa?se res?me stop co?nte? resta?t tncclr = 1; tnm [1:0] = 00 o?tp?t pin set to initial level low if tnoc=0 o?tp?t toggle with tnaf flag note tnio [1:0] = 10 active high o?tp?t select he?e tnio [1:0] = 11 toggle o?tp?t select o?tp?t not affected b? tnaf flag. remains high ?ntil ?eset b? tnon bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin-sha?ed f?nction o?tp?t inve?ts when tnpol is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow o?tp?t does not change compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=0 rev. 1.10 8 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 8? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom timer/counter mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t 0cclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t0dpx bit in the tm0c1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t0oc bit in the tm0c1 register is used to select the required polarity of the pwm waveform while the two t0io1 and t0io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t0pol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 56 ? 84 51 ? 640 ? 68 896 10 ? 4 d ? t ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125 khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra d ? t ? 1 ? 8 ? 56 ? 84 51 ? 640 ? 68 896 10 ? 4 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value. rev. 1.10 8? ?an?a?? 1?? ?01? rev. 1.10 8 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time co?nte? clea?ed b? ccrp pa?se res?me co?nte? stop if tnon bit low co?nte? reset when tnon ?et??ns high tndpx = 0; tnm [1:0] = 10 pwm d?t? c?cle set b? ccra pwm ?es?mes ope?ation o?tp?t cont?olled b? othe? pin-sha?ed f?nction o?tp?t inve?ts when tnpol = 1 pwm pe?iod set b? ccrp tm o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0 rev. 1.10 84 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 85 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time co?nte? clea?ed b? ccra pa?se res?me co?nte? stop if tnon bit low co?nte? reset when tnon ?et??ns high tndpx = 1; tnm [1:0] = 10 pwm d?t? c?cle set b? ccrp pwm ?es?mes ope?ation o?tp?t cont?olled b? othe? pin-sha?ed f?nction o?tp?t inve?ts when tnpol = 1 pwm pe?iod set b? ccra tm o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0 rev. 1.10 84 ?an?a?? 1?? ?01? rev. 1.10 85 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom enhanced type tm C etm the e nhanced t ype t m c ontains f ive o perating m odes, wh ich a re c ompare ma tch ou tput, timer/event counter , capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three external output pins. ctm name tm no. tm input pin tm output pin ht66f ? 0-1/ht68f ? 0-1 10-bit etm 1 tck1 tp1a; tp1b_0 ? tp1b_1 ? ? ? ?? ? ? ? - ? ? - ? ? ??? ?? ? - ? - ? - ? - ? ? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? ?? - ? ? ? ? ?- ? ?- ? ? ? ? ? ? ? ? ? ? ??? ?? ? ?- ? ?- ? ? - ? ? - ? ? ? enhanced type tm block diagram (n=1) enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock s ource. there are three internal comparators w ith the names, comparator a , comparator b and comparator p . these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the t1on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers. rev. 1.10 86 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 8? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 tm1c1 t1am1 t1am0 t1aio1 t1aio0 t1aoc t1paol t1cdn t1cclr tm1c ? t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1pbol t1pwm1 t1pwm0 tm1dl d ? d6 d5 d4 d ? d ? d1 d0 tm1dh d9 d8 tm1al d ? d6 d5 d4 d ? d ? d1 d0 tm1ah d9 d8 tm1bl d ? d6 d5 d4 d ? d ? d1 d0 tm1bh d9 d8 10-bit enhanced tm register list C ht66f30-1/HT68F30-1 tm1c0 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau: tm1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0: select tm1 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: reserved 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the clock source f is the system c lock, wh ile f a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. rev. 1.10 86 ?an?a?? 1?? ?01? rev. 1.10 8 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom bit 3 t1on: tm1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run and clearing the bit disables the tm. clearing this bit to zero will stop t he c ounter f rom c ounting a nd t urn o ff t he t m wh ich wi ll r educe i ts p ower consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0: tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 1cclr bi t i s se t t o zero. set ting t he t 1cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. rev. 1.10 88 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 89 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom tm1c1 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0: select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm shoul d be switche d of f be fore any changes are made to the t1am1 and t1am0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0: select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register . note that the output level requested by the t1aio1 and t1aio0 bits must be dif ferent from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running. rev. 1.10 88 ?an?a?? 1?? ?01? rev. 1.10 89 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom bit 3 t1aoc: tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol: tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 t1cdn: tm1 count up or down fag 0: count up 1: count down bit 0 t1cclr: select tm1 counter clear condition 0: tm1 comparatror p match 1: tm1 comparatror a match this bit is used to select the method which clears the counter . remember that the e nhanced t m c ontains t hree c omparators, com parator a, compara tor b a nd comparator p , but only comparator a or comparator p can be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implement ed if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. rev. 1.10 90 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 91 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom tm1c2 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1~t1bm0: select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the t m sh ould b e swi tched o ff b efore a ny c hanges a re m ade t o t he t 1bm1 a nd t1bm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0: select tp1b_0, tp1b_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1 01: input capture at falling edge of tp1b_0, tp1b_1 10: input capture at falling/rising edge of tp1b_0, tp1b_1 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator b. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator b. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register . note that the output level re quested by t he t 1bio1 a nd t 1bio0 bi ts m ust be di fferent from t he i nitial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in t he pwm mode , t he t 1bio1 a nd t 1bio0 bi ts de termine how t he t m out put pi n changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1bio1 and t1bio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running. rev. 1.10 90 ?an?a?? 1?? ?01? rev. 1.10 91 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom bit 3 t1boc: tp1b_0, tp1b_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol: tp1b_0, tp1b_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1~0 t1pwm1~t1pwm0: select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl: tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1dh: tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al: tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 rev. 1.10 9 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 9? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom tm1ah register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1ah: tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 tm1bl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1bl: tm1 ccrb low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 tm1bh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1bh: tm1 ccrb high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9~bit 8 enhanced type tm operating modes the enhanced t ype tm can operat e in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t1am1 and t1am0 bits in the tm1c1, and the t1bm1 and t1bm0 bits in the tm1c2 register. etm operation mode ccra compare match output mode ccra timer/counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode ccrb compa ? e match o ? tp ? t mode ccrb time ? /co ? nte ? mode ccrb pwm o ? tp ? t mode ccrb single p ? lse o ? tp ? t mode ccrb inp ? t capt ?? e mode ?: permitted; : not permitted rev. 1.10 9? ?an?a?? 1?? ?01? rev. 1.10 9 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom compare output mode to select this mode, bits t1am1, t1am0 and t1bm1, t1bm0 in the tm1c1/tm1c2 registers should be all clear ed to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p . when the t1cclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow. here both the t1af and t1pf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the t1cclr bit in the tm1c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t1af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t1cclr is high no t1pf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t1af or t1bf interrupt request fag is generated after a compare match occurs from comparator a or comparator b. the t1pf interrupt request flag, generated from a compare match from comparator p , will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the t1aio1 and t1aio0 bits in the tm1c1 register for etm ccra, and the t1bio1 and t1bio0 bits in the tm1c2 register for etm ccrb. the tm output pin can be selected using the t1aio1, t1aio0 bits (for the tp1a pin) and t1bio1, t1bio0 bits (for the tp1b_0, tp1b_1 pins) to go high, to go low or to toggl e from it s prese nt condi tion when a compare ma tch occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm output pin, is setup after the t1aoc or t1boc bit for tp1a or tp1b_0, tp1b_1 output pins. note that if the t1aio1, t1aio0 and t1bio1, t1bio0 bits are zero then no pin change will take place. rev. 1.10 94 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 95 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e 0x?ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccrp=0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed b? ccrp val?e pa?se res?me stop co?nte? resta?t tncclr = 0; tnam [1:0 ] = 00 o?tp?t pin set to initial level low if tnaoc =0 o?tp?t toggle with tnaf flag note tnaio [1:0 ] = 10 active high o?tp?t select he?e tnaio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected b? tnaf flag . remains high ?ntil ?eset b? tnon bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high etm ccra compare match output mode C tncclr=0 note: 1. w ith tncclr=0 the comparator p match will clear the counter 2. tpna output pin controlled only by tnaf fag 3. output pin reset to initial state by tnon bit rising edge 4. n=1 rev. 1.10 94 ?an?a?? 1?? ?01? rev. 1.10 95 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e 0x?ff ccrp ccrb tnon tnpau tnbpol ccrp int. flag tnpf ccrb int. flag tnbf tpnb o/p pin time ccrp=0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed b? ccrp val?e pa?se res?me stop co?nte? resta?t tncclr = 0; tnbm [1:0 ] = 00 o?tp?t pin set to initial level low if tnboc =0 o?tp?t toggle with tnbf flag note tnbio [1:0 ] = 10 active high o?tp?t select he?e tnbio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected b? tnbf flag . remains high ?ntil ?eset b? tnon bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnbpol is high etm ccrb compare match output mode C tncclr=0 note: 1. w ith tncclr=0 the comparator p match will clear the counter 2. tpnb output pin controlled only by tnbf fag 3. output pin reset to initial state by tnon bit rising edge 4. n=1 rev. 1.10 96 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 9? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e 0x?ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed b? ccra val?e pa?se res?me stop co?nte? resta?t tncclr = 1; tnam [1:0 ] = 00 o?tp?t pin set to initial level low if tnaoc =0 o?tp?t toggle with tnaf flag note tnaio [1:0 ] = 10 active high o?tp?t select he?e tnaio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected b? tnaf flag . remains high ?ntil ?eset b? tnon bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow o?tp?t does not change etm ccra compare match output mode C tncclr=1 note: 1. w ith tncclr=1 the comparator a match will clear the counter 2. tpna output pin controlled only by tnaf fag 3. tpna output pin reset to initial state by tnon rising edge 4. tnpf fags not generated when tncclr=1 5. n=1 rev. 1.10 96 ?an?a?? 1?? ?01? rev. 1.10 9 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e 0x?ff ccrb ccra tnon tnpau tnbpol ccrb int. flag tnbf ccra int. flag tnaf tpnb o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed b? ccra val?e pa?se res?me stop co?nte? resta?t tncclr = 1; tnbm [1:0 ] = 00 o?tp?t pin set to initial level low if tnboc =0 o?tp?t toggle with tnbf flag note tnbio [1:0 ] = 10 active high o?tp?t select he?e tnbio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected b? tnbf flag . remains high ?ntil ?eset b? tnon bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnbpol is high no tnaf flag gene?ated on ccra ove?flow etm ccrb compare match output mode C tncclr=1 note: 1. w ith tncclr=1 the comparator a match will clear the counter 2. tpnb output pin controlled only by tnbf fag 3. tpnb output pin reset to initial state by tnon rising edge 4. tnpf fags not generated when tncclr=1 5. n=1 timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the p wm function w ithin the tm is us eful for applications w hich require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. rev. 1.10 98 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 99 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extre mely fexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. w ith the tncclr bit set high, the pwm period can be fnely controlled using the ccra register s. in this case the ccrb registers are used to set the pwm duty value (for t pnb out put pi ns). t he ccrp bi ts a re not use d a nd t pna out put pi n i s not use d. t he pwm output can only be generated on the tpnb output pins. w ith the tncclr bit cleared to zero, the pwm pe riod is set usi ng one of the eight va lues of the three ccrp bi ts, in multiples of 128. now b oth c cra a nd c crb r egisters c an b e u sed t o se tup d ifferent d uty c ycle v alues t o p rovide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. w ith all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially , thus reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp , will be generated when a compare match occurs from ei ther the com parator a, com parator b or com parator p . the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform. etm, pwm mode, edge C aligned mode, t1cclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 56 ? 84 51 ? 640 ? 68 896 10 ? 4 a d ? t ? ccra b d ? t ? ccrb if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128 and ccrb=256, the tp1a pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. the tp1b_n pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=256/512=50%. if t he duty value defned by the ccra or ccrb re gister i s e qual to or gre ater t han the period value, then the pwm output duty is 100%. etm, pwm mode, edge C aligned mode, t1cclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe ? iod 1 ? ? 511 51 ? 10 ? 1 10 ?? 10 ?? b d ? t ? ccrb etm, pwm mode, center C aligned mode, t1cclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ? 56 51 ? ? 68 10 ? 4 1 ? 80 15 ? 6 1 ? 9 ? ? 046 a d ? t ? (ccra ? ) - 1 b d ? t ? (ccrb ? ) - 1 rev. 1.10 98 ?an?a?? 1?? ?01? rev. 1.10 99 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom etm, pwm mode, center C aligned mode, t1cclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe ? iod ? 4 6 10 ?? 10 ? 4 ? 04 ? ? 044 ? 046 b d ? t ? (ccrb ? ) - 1 co?nte? val?e ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc =1) time co?nte? clea?ed b? ccrp pa?se res?me stop co?nte? resta?t tncclr = 0; tnam [1:0 ] = 10 ? tnbm [1:0 ] = 10 ; tnpwm [1:0 ] = 00 o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set b? ccra d?t? c?cle set b? ccrb pwm pe?iod set b? ccrp d?t? c?cle set b? ccra d?t? c?cle set b? ccra etm pwm mode C edge aligned note: 1. here tncclr=0 therefore ccrp clears counter and determines pwm period 2. internal pwm function continues even when tnaio [1:0] (or tnbio [1:0])=00 or 01 3. ccra controls tpna pwm duty and ccrb controls tpnb pwm duty 4. n=1 rev. 1.10 100 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 101 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e ccra tnon tnpau tnbpol ccrb int . flag tnbf time co?nte? clea?ed b? ccra pa?se res?me stop co?nte? resta?t tncclr = 1; tnbm [1:0 ] = 10 ; tnpwm [1:0 ] = 00 o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnbpol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set b? ccrb pwm pe?iod set b? ccra etm pwm mode C edge aligned note: 1. here tncclr=1 therefore ccra clears counter and determines pwm period 2. internal pwm function continues even when tnbio [1:0]=00 or 01 3. ccra controls tpnb pwm period and ccrb controls tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin 5. n=1 rev. 1.10 100 ?an?a?? 1?? ?01? rev. 1.10 101 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc =1) time pa?se res?me stop co?nte? resta?t tncclr = 0; tnam [1:0 ] = 10 ? tnbm [1:0 ] = 10 ; tnpwm [1:0 ] = 11 o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set b? ccra d?t? c?cle set b? ccrb pwm pe?iod set b? ccrp etm pwm mode C centre aligned note: 1. here tncclr=0 therefore ccrp clears counter and determines pwm period 2. tnpwm1/tnpwm0=1 1 therefore pwm is centre aligned 3. internal pwm function continues even when tnaio [1:0] (or tnbio [1:0])=00 or 01 4. ccra controls tpna pwm duty and ccrb controls tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value 6. n=1 rev. 1.10 10 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 10? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e ccra tnon tnpau tnbpol ccra int . flag tnaf ccrb int . flag tnbf time pa?se res?me stop co?nte? resta?t tncclr = 1 ; tnbm [1:0 ] = 10; tnpwm [1:0 ] = 11 o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin - sha?ed f?nction ccrb tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set b? ccrb pwm pe?iod set b? ccra o?tp?t inve?ts when tnbpol is high ccrp int . flag tnpf etm pwm mode C centre aligned note: 1. here tncclr=1 therefore ccra clears counter and determines pwm period 2. tnpwm1/tnpwm0=1 1 therefore pwm is centre aligned 3. internal pwm function continues even when tnbio [1:0]=00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value 6. n=1 rev. 1.10 10? ?an?a?? 1?? ?01? rev. 1.10 10 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom single pulse mode to select this mode, the required bit pairs, t1am1, t1am0 and t1bm1, t1bm0 should be set to 10 respectively and also the corresponding t1aio1, t1aio0 and t1bio1, t1bio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tp1a output leading edge is a low to high transition of the t1on bit, which can be implemented using the application program. the trigger for the pulse tp1b output leading edge i s a c ompare m atch fr om c omparator b , wh ich c an b e i mplemented u sing t he a pplication program. howe ver i n t he si ngle pul se mod e, t he t 1on bi t c an a lso be m ade t o a utomatically change from low to high using the external tck1 pin, whi ch will in turn init iate the singl e pulse output of tp1a. when the t1on bit transitions to a high level, the counter will start running and the pulse leading edge of tp1a will be generated. the t1on bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tp1a and tp1b will be generated when the t1on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the t1on bit and thus generate the single pulse output trailing edge of tp1a and tp1b. in this way the ccra value can be u sed t o c ontrol t he p ulse wi dth o f t p1a. t he c cra-ccrb v alue c an b e u sed t o c ontrol t he pulse widt h of t p1b. a c ompare m atch from com parator a a nd com parator b wil l a lso ge nerate tm inter rupts. the counter can only be reset back to zero when the t1on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t1cclr bit is also not used. s/w command settnon o? tckn pin t?ansition ccrb leading edge ccra t?ailing edge s/w command clrtnon o? ccra compa?e match tpna o?tp?t pin tpnb o?tp?t pin p? lse width = (ccra-ccrb) val?e p?lse width = ccra val?e co?nte? val?e ccrb ccra 0 time tnon = 1 ccrb compa?e match s/w command clrtnon o? ccra compa?e match ccrb t?ailing edge ccra leading edge tnon bit 1 0 tnon bit 1 0 tnon bit 0 1 single pulse generation (n=1) rev. 1.10 104 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 105 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e ccrb ccra tnon tnpau tnapol ccrb int. flag tnbf ccra int. flag tnaf tpna pin ( tnaoc =1) time co?nte? stopped b? ccra pa?se res?me co?nte? stops b? softwa?e co?nte? reset when tnon ?et??ns high tnam [1:0 ] = 10 ? tnbm [1:0 ] = 10 ; tnaio [1:0 ] = 11 ? tnbio [1:0 ] = 11 p?lse width set b? ( ccra -ccrb ) o?tp?t inve?ts when tnbpol =1 tckn pin softwa?e t?igge? clea?ed b? ccra match tckn pin t?igge? a?to. set b? tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? tnbpol tpna pin ( tnaoc =0) tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) p?lse width set b? ccra o?tp?t inve?ts when tnapol =1 etm C single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 11 and can not be changed. 6. n=1 rev. 1.10 104 ?an?a?? 1?? ?01? rev. 1.10 105 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom capture input mode to select this mode bits t1am1, t1am0 and t1bm1, t1bm0 in the tm1c1 and tm1c2 registers should be set to 01 respectively . this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the ext ernal si gnal i s suppli ed on t he tp1a and tp1b_0, tp1b_1 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t 1aio1, t 1aio0 and t 1bio1, t 1bio0 bits in the t m1c1 and tm1c2 registers. the counter is started when the t1on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp1a and tp1b_0, tp1b_1 pins the present value in the counter w ill be latched into the ccra and ccrb regis ters and a tm interrupt generated. irrespective of what events occur on the tp1a and tp1b_0, tp1b_1 pins the counter will continue to free run until the t1on bit changes from high to low . when a ccrp compare match occurs the counter wi ll rese t bac k t o z ero; i n t his wa y t he ccrp val ue c an be use d t o c ontrol t he m aximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. count ing the number of ove rfow int errupt signal s from the ccrp can be a useful method in measuring long pulse widths. the t1aio1, t1aio0 and t1bio1, t1bio0 bits can select the active trigger edge on the tp1a and tp1b_0, tp1b_1 pins to be a rising edge, falling edge or both edge types. if the t1aio1, t1aio0 and t1bio1, t1bio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp1a and tp1b_0, tp1b_1 pins, however it must be noted that the counter will continue to run. as t he t p1a a nd t p1b_0, t p1b_1 pi ns a re pi n sha red wit h ot her funct ions, c are m ust be t aken if the tm is in the capture input m ode. this is because if the pin is s etup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t1cclr, t1aoc, t1boc, t1apol and t1bpol bits are not used in this mode. rev. 1.10 106 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 10? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom co?nte? val?e yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra val?e time co?nte? clea?ed b? ccrp pa?se res?me co?nte? reset tnam [1:0 ] = 01 tm capt??e pin tpna xx co?nte? stop tnaio [1:0] val?e xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capt??e etm ccra capture input mode note: 1. t1am [1:0] = 01 and active edge set by the t1aio [1:0] bits 2. tm capture input pin active edge transfers counter value to ccra 3. tncclr bit not used 4. no output function C tnaoc and tnapol bits not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n=1 rev. 1.10 106 ?an?a?? 1?? ?01? rev. 1.10 10 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ccrp co?nte? ove?flow ccrp int. flag tnpf ccrb int. flag tnbf tnon bit pa ?se co ?n te? re set tnpau bit res? me sto p yy xx ccrb val?e xx tm capt??e pin yy tnbio1? tnbio0 val?e 00 - rising edge 01 - falling edge 11 - disable capt??e active edge ac ti ve edge xx 10 - both edges active edges yy tnbm1? tnbm0 = 01 tim e co?nte? val?e etm ccrb capture input mode note: 1. tnbm [1:0]=01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. the tncclr bit is not used 4. no output function C tnboc and tnbpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n=1 rev. 1.10 108 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 109 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the ht66f30-1 contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. part no. input channels a/d channel select bits input pins ht66f ? 0-1 8 acs4 ? acs ? ~acs0 an0~an ? the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d ? d ? d1 d0 adrl(adrfs=1) d ? d6 d5 d4 d ? d ? d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d ? d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs ? acs1 acs0 adcr1 acs4 v1 ? 5en vrefs adck ? adck1 adck0 acerl ace ? ace6 ace5 ace4 ace ? ace ? ace1 ace0 ht66f30-1 a/d converter register list ? ? ? ? ?? ? ? ? ? ? ? -? ? ? ?? ? ? ? ? ? ? ? ?? ? a/d converter structure rev. 1.10 108 ?an?a?? 1?? ?01? rev. 1.10 109 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom a/d converter data registers C adrl, adrh as the ht66f30-1 contains an inte rnal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as adrh, and a low byte register , known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d ? d6 d5 d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d ? d6 d5 d4 d ? d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 a nd acerl a re provide d. t hese 8-bi t re gisters de fne func tions such a s t he sel ection of which analog channel is connected to the internal a/d converter , the digitised data format, the a/d cloc k source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs2~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register define the adc input channel number . as the devices contain only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter . it is the function of the acs4 and acs2~acs0 bits to determine which analog channel input pins or internal 1.25v is actually connected to the internal a/d converter. the acerl control register contains the ace7~ace0 bits which determine which pins on port a is used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. rev. 1.10 110 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 111 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom adcr0 register ? ht66f30-1 bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 start: start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs: adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as "0" bit 2~0 acs2, acs1, acs0: select a/d channel (when acs4 is 0) 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter. rev. 1.10 110 ?an?a?? 1?? ?01? rev. 1.10 111 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 v1 ? 5en vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4: select internal 1.25v bandgap voltage as adc input 0: disable 1: enable this bit enables the1.25v bandgap voltage to be connected to the a/d converter . the v125en bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter . when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125en: internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap voltage 1.25v can be used as an a/d converter input. if the bandgap voltage 1.25v is not used by the a/d converter and the lvr/lvd function is disable d then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as "0" bit 4 vrefs: select adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as "0" bit 2~0 adck2, adck1, adck0: select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter. rev. 1.10 11 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 11 ? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom acerl register bit 7 6 5 4 3 2 1 0 name ace ? ace6 ace5 ace4 ace ? ace ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7: defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6: defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5: defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4: defne pa4 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3: defne pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2: defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1: defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0: defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate when t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow to t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. rev. 1.10 11 ? ?an?a?? 1?? ?01? rev. 1.10 11 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom although the a/d clock source is determined by the system clocky , f sys , and by bits adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t adck , is 0.5s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000. doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s 32s 64s undefned ? mhz 500ns 1s 2s 4s 8s 16s 32s undefned 4mhz ? 50ns* 500ns 1s 2s 4s 8s 16s undefned 8mhz 1 ? 5ns* ? 50ns* 500ns 1s 2s 4s 8s undefned 1 ? mhz 8 ? ns* 16 ? ns* ??? ns* 66 ? ns 1.33s 2.67s 5.33s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . even if no pins are selected for use as a/d inputs by clearing the ace7~ace0 bits in the acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of t he a/ d a nalog i nput pi ns a re pi n-shared wi th t he i/ o pi ns on por t a a s we ll a s ot her functions. the ace7~ace0 bits in the acerl register , determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace7~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r func tions. al l pull -high resi stors, whi ch are se tup t hrough register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that i t i s not ne cessary t o frst se tup t he a/ d pi n a s a n i nput i n t he p ac por t c ontrol re gisters t o enable t he a/ d i nput as when t he ace 7~ace0 bit s ena ble an a/ d i nput, t he st atus of t he port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref . rev. 1.10 114 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 115 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ?? ? ? - a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4, acs2~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace7~ace0 bits in the acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when t his bit goes l ow. when thi s occurs the a/d data register adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16t adck where t adck is equal to the a/d clock period. rev. 1.10 114 ?an?a?? 1?? ?01? rev. 1.10 115 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ?? ? ? ??? ? -?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the ht66f30-1 contains a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb=(v dd or v ref )4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (v dd or v ref )4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level. rev. 1.10 116 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 11 ? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ? ? ?? ? ? ? ideal a/d transfer function a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov adcr1,a ; s elect f sys /8 as a /d c lock a nd s witch o ff 1 .25v clr adoff mov a,0fh ; s etup a cerl t o c onfgure p ins a n0~an3 mov acerl,a mov a,00h mov adcr0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : start_conversion: clr st art ; h igh p ulse o n s tart b it t o i nitiate c onversion set s tart ; r eset a /d clr s tart ; s tart a /d polling_eoc: sz eocb ; p oll t he a dcr0 r egister e ocb b it t o d etect e nd ; o f a /d c onversion jmp p olling_eoc ; c ontinue p olling mov a ,adrl ; re ad l ow b yte c onversion re sult v alue mov a drl_buffer,a ; s ave r esult t o us er d efned r egister mov a ,adrh ; re ad h igh b yte c onversion re sult v alue mov a drh_buffer,a ; s ave r esult t o us er d efned r egister : : jmp start_conversion ; st art n ext a/d c onversion rev. 1.10 116 ?an?a?? 1?? ?01? rev. 1.10 11 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom example: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov adcr1,a ; s elect f sys /8 as a /d c lock a nd s witch o ff 1 .25v clr adoff mov a,0fh ; s etup a cerl t o c onfgure p ins a n0~an3 mov acerl,a mov a,00h mov adcr0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter start_conversion: clr st art ; h igh p ulse o n st art b it t o i nitiate c onversion set s tart ; r eset a /d clr s tart ; s tart a /d clr a df ; c lear a dc i nterrupt re quest f ag s et ade ; enable adc interrupt set e mi ; e nable gl obal i nterrupt : : ; adc interrupt service routine adc_isr: mov ac c_stack,a ; s ave a cc t o u ser d efned m emory mov a ,status mov s tatus_stack,a ; s ave st atus t o us er d efned m emory : : mov a ,adrl ; re ad l ow b yte c onversion re sult v alue mov a drl_buffer,a ; s ave r esult t o us er d efned r egister mov a ,adrh ; re ad h igh b yte c onversion re sult v alue mov a drh_buffer,a ; s ave r esult t o us er d efned r egister : : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore s tatus f rom u ser d efned m emory mov a ,acc_stack ; r estore a cc fr om u ser d efned m emory reti rev. 1.10 118 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 119 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom comparators two independent analog comparators are contained within these devices. these functions of fer fexibility via their register controlled features such as power -down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. comparator comparator operation the de vices c ontain t wo c omparator fu nctions whi ch a re u sed t o c ompare t wo a nalog v oltages and provide an output based on their dif ference. full control over the two internal comparators is provided via two control registers, cp0c and cp1c, one assigned to each comparator . the comparator output is recorded via a bit in their respective control register , but can also be transferred out o nto a sh ared i/ o p in. add itional c omparator fu nctions i nclude, o utput p olarity, h ysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, so me sp urious o utput si gnals m ay b e g enerated o n t he c omparator o utput d ue t o t he sl ow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator . ideally the comparator should swi tch a t t he poi nt whe re t he posi tive a nd ne gative i nputs si gnals a re a t t he sa me vol tage level, however , unavoidable input of fsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator registers there are two registers for overall comparator operation, one for each comparator . as corresponding bits in the tw o registers have identical functions , they following register table applies to both registers. register name bit 7 6 5 4 3 2 1 0 cp0c c0sel c0en c0pol c0out c0os c0hyen cp1c c1sel c1en c1pol c1out c1os c1hyen comparator registers list rev. 1.10 118 ?an?a?? 1?? ?01? rev. 1.10 119 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom cp0c register bit 7 6 5 4 3 2 1 0 name c0sel c0en c0pol c0out c0os c0hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c0sel: select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c0en: comparator on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are appli ed to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the sleep or idle mode. bit 5 c0pol: comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c0out bit will refect the non-inverted output condition of the comparator . if the bit is high the comparator c0out bit will be inverted. bit 4 c0out: comparator output bit c0pol=0 0: c0+ < c0- 1: c0+ > c0- c0pol=1 0: c0+ > c0- 1: c0+ < c0- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c0pol bit. bit 3 c0os: output path select 0: c0x pin 1: internal use this is the comparator output path select control bit. if the bit is set to "0" and the c0sel bit is "1" the comparator output is connected to an external c0x pin. if the bit is set to "1" or the c0sel bit is "0" the comparator output signal is only used internally by the devices allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as "0" bit 0 c0hyen: hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold. rev. 1.10 1 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?1 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom cp1c register bit 7 6 5 4 3 2 1 0 name c1sel c1en c1pol c1out c1os c1hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c1sel: select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c1en: comparator on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the sleep or idle mode. bit 5 c1pol: comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c1out bit will refect the non-inverted output condition of the comparator . if the bit is high the comparator c1out bit will be inverted. bit 4 c1out: comparator output bit c1pol=0 0: c1+ < c1- 1: c1+ > c1- c1pol=1 0: c1+ > c1- 1: c1+ < c1- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c1pol bit. bit 3 c1os: output path select 0: c1x pin 1: internal use this is the comparator output path select control bit. if the bit is set to "0" and the c1sel bit is "1" the comparator output is connected to an external c1x pin. if the bit is set to "1" or the c1sel bit is "0" the comparator output signal is only used internally by the devices allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as "0" bit 0 c1hyen: hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold. rev. 1.10 1?0 ?an?a?? 1?? ?01? rev. 1.10 1 ? 1 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom comparator interrupt each a lso possesses i ts own i nterrupt func tion. w hen a ny one of t he c hanges sta te, i ts re levant interrupt fl ag will be set, and if the corresponding int errupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the c0out or c1out bit and not the output pin w hich generates an interrupt. if the microcontroller is in the s leep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power , the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. serial interface module C sim these devices contain a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory , etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must frst be selected using a confguration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register . these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers, and also if the sim function is enabled. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a si ngle m aster, but t hese de vices provi ded onl y one scs pi n. if t he m aster ne eds t o c ontrol multiple slave devices from a single master, the master can use i/o pin to select the slave devices. rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines , s ck is the s erial clock line and scs is the s lave s elect line. a s the sp i interface pins are pin-shared with other functions and with the i 2 c function pins, the spi interface must frst be selected by the correct bits in the simc0 and simc2 registers. after the spi option has been selected, it can also be additionally disabled or enabled using the simen bit in the simc0 register . communication be tween de vices c onnected t o t he spi i nterface i s c arried out i n a sl ave/master mode wi th a ll d ata t ransfer i nitiations b eing i mplemented b y t he m aster. t he ma ster a lso c ontrols the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be foating state. spi master/slave connection ? ? ? ? ? ? ? ? ? ? - ? ? ? ? ? ? ?? ? ? spi bolck diagram rev. 1.10 1?? ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom the spi function in these devices offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? wcol bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the devices are in the master or slave mode and upon the condition of certain control bits such as csen and simen. there are s everal configuration options ass ociated w ith the s pi interface. o ne of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no ef fect. another two spi confguration options determine if the csen and wcol bits are to be used. spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simd d ? d6 d5 d4 d ? d ? d1 d0 simc ? d ? d6 ckpolb ckeg mls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the devices write data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the devices can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. al though not c onnected wi th t he spi function, the simc0 register is also used to control the peripheral clock prescaler . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. rev. 1.10 1 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?5 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from tm0. if the spi slave mode is selected then the clock will be supplied by an external master devices. bit 4 pcken: pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0: select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen: sim control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0" rev. 1.10 1?4 ?an?a?? 1?? ?01? rev. 1.10 1 ? 5 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom simc2 register bit 7 6 5 4 3 2 1 0 name d ? d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by the application program. bit 5 ckpolb: determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t determines the ba se condition of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg: determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inact ive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls: spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen: spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into i/o pin or the other functions. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or enabled via confguration option. bit 1 wcol: spi w rite collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cle ared by the applic ation program. note that using the wcol bit can be disabled or enabled via confguration option. bit 0 trf: spi t ransmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt. rev. 1.10 1 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd re gister. t he m aster shoul d out put a n scs si gnal t o e nable t he sl ave de vices be fore a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode. ? ? ? ? ? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ? ? ? spi master mode timing ? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg=0 rev. 1.10 1?6 ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ??? ? ? ? ? ? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ? ? ? ?? ?? ?? ? ? ?? ?? ??? ? ?? ? ? ? ? ? ? ?? spi slave mode timing C ckeg=1 ? ? ? ? ? ? ? ? ? ? ? - ? ?? ? ? ? ? ? ? ?? ?? ? ?? ? ??????? ?? ? ?? ?? ? spi transfer control flowchart rev. 1.10 1 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?9 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several confguration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. a c onfguration op tion e xists t o a llow a c lock ot her t han t he syst em c lock t o dr ive t he i 2 c interface. another confguration option determines the debounce time of the i 2 c interface. this uses the internal clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. t he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. t o achieve the required i 2 c data trans fer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no debo ? nce f sys > ? mhz f sys > 5mhz ? s ? stem clock debo ? nce f sys > 4mhz f sys > 10mhz 4 s ? stem clock debo ? nce f sys > 8mhz f sys > ? 0mhz i 2 c minimum f sys frequency rev. 1.10 1?8 ?an?a?? 1?? ?01? rev. 1.10 1 ? 9 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima, and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the micro controller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf hans hbb htx txak srw iamwu rxak simd d ? d6 d5 d4 d ? d ? d1 d0 sima iica6 iica5 iica4 iica ? iica ? iica1 iica0 d0 i 2 c registers list rev. 1.10 1 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?1 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken: pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0: select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen: sim control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bi t changes from low to hi gh and should therefore be frst initial ised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0" rev. 1.10 1?0 ?an?a?? 1?? ?01? rev. 1.10 1 ? 1 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf: i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas: i 2 c bus address match fag 0: not address match 1: address match the hass fag i s t he a ddress m atch fag. t his fag i s used t o de termine i f t he sla ve device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb: i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx: select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak: i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw: i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu: i 2 c address match w ake-up control 0: disable 1: enable - must be cleared by the application program after wake-up this bit should be set to 1 to enabl e the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom bit 0 rxak: i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave does not receive acknowledge fag the r xak fl ag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s 0, i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the devices write data to the spi bus, the actual data to be trans mitted mus t be placed in the s imd regis ter. a fter the data is received from the spi bus, the devices can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown sima register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica ? iica ? iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x "x" ? nknown bit 7~1 iica6~iica0: i 2 c slave address iica6~iica0 is the i 2 c slave address bit 6~bit 0. the si ma r egister i s a lso u sed b y t he spi i nterface b ut h as t he n ame si mc2. t he sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register define the device slave address . bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program. rev. 1.10 1?? ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ? ?-? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? i 2 c block diagram i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt. rev. 1.10 1 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?5 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ? ? - ?? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart i 2 c bus start signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, t he haas bi t shoul d be e xamined t o se e whe ther t he i nterrupt sourc e ha s c ome from a matching slave address or from the completion of a data byte transfer . when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. rev. 1.10 1?4 ?an?a?? 1?? ?01? rev. 1.10 1 ? 5 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom i 2 c bus read/write signal the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0. i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowle dge signal, level 0, before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register . if setup as a receive r, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. rev. 1.10 1 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? ? ? ? ? ? ? ? - ? - ? ? note: *when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram ? ? ? ? i 2 c bus isr fow chart rev. 1.10 1?6 ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register . the peripheral clock function is controlled using the simc0 register . the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/of f control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit to "0" disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken: pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0: select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen: sim control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. whe n the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be first initialised by the application program. bit 0 unimplemented, read as "0" rev. 1.10 1 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?9 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. these devices contain several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int 0~int1 and pint pi ns, whi le the internal interrupts are ge nerated by various internal functions such as the tms, comparators,time base, lvd, eeprom, sim and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc1 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble individual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi compa ? ato ? cpne cpnf n=0 o ? 1 intn pin intne intnf n=0~1 a/d conve ? te ? ade adf ht66f ? 0-1 onl ? m ? lti-f ? nction mfne mfnf n=0~ ? time base tbne tbnf n=0 o ? 1 sim sime simf lvd lve lvf eeprom dee def pint pin xpe xpf tm tnpe tnpf n=0~1 tnae tnaf tnbe tnbf n=1 interrupt register bit naming conventions rev. 1.10 1?8 ?an?a?? 1?? ?01? rev. 1.10 1 ? 9 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom interrupt register contents ? ht66f30-1 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 adf mf1f mf0f cp1f ade mf1e mf0e cp1e intc ? mf ? f tb1f tb0f mf ? f mf ? e tb1e tb0e mf ? e mfi0 t0af t0pf t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi ? def lvf xpf simf dee lve xpe sime ? HT68F30-1 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 mf1f mf0f cp1f mf1e mf0e cp1e intc ? mf ? f tb1f tb0f mf ? f mf ? e tb1e tb0e mf ? e mfi0 t0af t0pf t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi ? def lvf xpf simf dee lve xpe sime integ register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0 bit 3~2 int1s1, int1s0: interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0: interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges rev. 1.10 140 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 141 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom intc0 register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name cp0f int1f int0f cp0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 cp0f: comparator 0 interrupt request flag 0: no request 1: interrupt request bit 5 int1f: int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f: int0 interrupt request fag 0: no request 1: interrupt request bit 3 cp0e: comparator 0 interrupt control 0: disable 1: enable bit 2 int1e: int1 interrupt control 0: disable 1: enable bit 1 int0e: int0 interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable rev. 1.10 140 ?an?a?? 1?? ?01? rev. 1.10 141 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom intc1 register ? ht66f30-1 bit 7 6 5 4 3 2 1 0 name adf mf1f mf0f cp1f ade mf1e mf0e cp1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf: a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf1f: multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 5 mf0f: multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 4 cp1f: comparator 1 interrupt request flag 0: no request 1: interrupt request bit 3 ade: a/d converter interrupt interrupt control 0: disable 1: enable bit 2 mf1e: multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e: multi-function interrupt 0 control 0: disable 1: enable bit 0 cp1e: comparator 1 interrupt control 0: disable 1: enable rev. 1.10 14 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 14? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ? HT68F30-1 bit 7 6 5 4 3 2 1 0 name mf1f mf0f cp1f mf1e mf0e cp1e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplenented, read as "0" bit 6 mf1f: multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 5 mf0f: multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 4 cp1f: comparator 1 interrupt request flag 0: no request 1: interrupt request bit 3 unimplenented, read as "0" bit 2 mf1e: multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e: multi-function interrupt 0 control 0: disable 1: enable bit 0 cp1e: comparator 1 interrupt control 0: disable 1: enable rev. 1.10 14? ?an?a?? 1?? ?01? rev. 1.10 14 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom intc2 register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name mf ? f tb1f tb0f mf ? f mf ? e tb1e tb0e mf ? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f: multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 6 tb1f: t ime base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f: t ime base 0 interrupt request flag 0: no request 1: interrupt request bit 4 mf2f: multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 3 mf3e: multi-function interrupt 3 control 0: disable 1: enable bit 2 tb1e: t ime base 1 interrupt control 0: disable 1: enable bit 1 tb0e: t ime base 0 interrupt control 0: disable 1: enable bit 0 mf2e: multi-function interrupt 2 control 0: disable 1: enable rev. 1.10 144 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 145 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom mfi0 register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name t1bf t1af t1pf t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 t1bf: tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 t1be: tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable rev. 1.10 144 ?an?a?? 1?? ?01? rev. 1.10 145 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom mfi2 register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name def lvf xpf simf dee lve xpe sime r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 def: data eeprom interrupt request fag 0: no request 1: interrupt request bit 6 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 5 xpf: external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 simf: sim interrupt request fag 0: no request 1: interrupt request bit 3 dee: data eeprom interrupt control 0: disable 1: enable bit 2 lve: lvd interrupt control 0: disable 1: enable bit 1 xpe: external peripheral interrupt control 0: disable 1: enable bit 0 sime: sim interrupt control 0: disable 1: enable rev. 1.10 146 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 14? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom interrupt operation when the conditio ns for an interrupt event occur , such as a tm compare p , compare a or compare b match or a/d conversion comple tion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. rev. 1.10 146 ?an?a?? 1?? ?01? rev. 1.10 14 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 04h 08h 0ch 10h 14h 18h 1ch ?0h ?4h ?8h vector low p ? io ? it ? high req ? est flags enable bits maste ? e nable req ? est flags enable bits emi a ? to disabled in isr inte ??? pts contained within m? lti - f ? nction inte ??? pts inte ??? pt name inte ??? pt name mf ?f m. f ? nct . ? mf ?e xpf pint pin xpe emi ? ch lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe t0af tm0 a t0ae t0pf tm0 p t0pe int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. f ? nct . 0 mf0e mf1f m. f ? nct . 1 mf1e adf a/d ade emi mf ?f m. f ? nct . ? mf ?e tb0f time base 0 tb0e tb1f time base 1 tb1e xxf legend req ? est flag C no a ? to ? eset in isr xxf req ? est flag C a? to ? eset in isr xxe enable bit interrupt structure C ht66f30-1 rev. 1.10 148 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 149 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 04h 08h 0ch 10h 14h 18h ?0h ?4h ?8h vector low p ? io ? it ? high req ? est flags enable bits maste ? enable req ? est flags enable bits emi a ? to disabled in isr inte ??? pts contained within m? lti - f ? nction inte ??? pts inte ??? pt name inte ??? pt name mf ?f m. f ? nct . ? mf ?e xpf pint pin xpe emi ? ch lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe t0af tm0 a t0ae t0pf tm0 p t0pe int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. f ? nct . 0 mf0e mf1f m. f ? nct . 1 mf1e mf ?f m. f ? nct . ? mf ?e tb0f time base 0 tb0e tb1f time base 1 tb1e xxf legend req ? est flag C no a ? to ? eset in isr xxf req ? est flag C a? to ? eset in isr xxe enable bit interrupt structure C HT68F30-1 rev. 1.10 148 ?an?a?? 1?? ?01? rev. 1.10 149 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom external interrupt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator interrupts are controlled by the two internal comparators. a comparator interrupt request will take place when the comparator interrupt request flags, cp0f or cp1f , are set, a situation that will occur when the comparator output changes state. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bits, cp0e and cp1e, must frst be set. when the inte rrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector , will take place. when the interrupt is serviced, the comparator interrupt request fags, cp0f and cp1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within t hese d evices a re f our mu lti-function i nterrupts. un like t he o ther i ndependent i nterrupts, these int errupts have no i ndependent sourc e, but rat her are form ed from other exi sting i nterrupt sources, namely the tm interrupts, sim interrupt, external peripheral interrupt, l vd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf3f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, sim interrupt, external peripheral interrupt, l vd interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program. rev. 1.10 150 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 151 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. rev. 1.10 150 ?an?a?? 1?? ?01? rev. 1.10 151 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon: tb0 and tb1 control 0: disable 1: enable bit 6 tbck: select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10: select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp: lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00: select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb ? ? ? time base interrupts rev. 1.10 15 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 15? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom serial interface module interrupts the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function interrupt. a sim interrupt request will take place when the sim interrupt request fag, simf , is set, which occurs when a byte of data has been received or transmitted by the sim interface. t o allow the program to branch to its res pective interrupt vector addres s, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, and muti-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective multi-function interrupt vector , will take place. when the serial interface interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the simf fag will not be automatically cleared, it has to be cleared by the application program. external peripheral interrupt the exte rnal peripheral interrupt operates in a similar way to the exter nal interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf , is set, which occurs when a negative edge transition appears on the pint pin. t o allow the program to branch to its respective interrupt vector address, the global i nterrupt e nable bi t, e mi, e xternal pe ripheral i nterrupt e nable bi t, xpe , a nd a ssociated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full a nd a ne gative t ransition a ppears on t he e xternal peri pheral int errupt pi n, a subrout ine c all t o the re spective mu lti-function int errupt, wi ll t ake pl ace. w hen t he e xternal pe ripheral int errupt i s serviced, t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts, ho wever on ly t he multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automa tically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with dif ferent functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin. eeprom interrupt the eep rom interrupt, is contained w ithin the m ulti-function interrupt. a n eep rom interrupt request will take place when the eeprom interrupt request fag, def , is set, which occurs when an eeprom write or read cycle ends. t o allow the program to branch to its respective interrupt vector address, t he g lobal i nterrupt e nable b it, e mi, e eprom i nterrupt e nable b it, de e, a nd a ssociated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full a nd a n e eprom wr ite o r r ead c ycle e nds, a su broutine c all t o t he r espective mu lti-function interrupt vector , will take place. when the eeprom interrupt is serviced, the emi bit will be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. rev. 1.10 15? ?an?a?? 1?? ?01? rev. 1.10 15 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact tm has two interrupts, while the enhanced t ype tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for the compact t ype tm there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced t ype tm there are three interrupt request fags tnpf , tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt reques t w ill take place w hen any of the tm reques t fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep o r i dle mo de. a wa ke-up i s g enerated wh en a n i nterrupt r equest fa g c hanges f rom l ow to high and is independent of whether the interrupt is enabled or not. therefore, even though these devices are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fl ag to be set hi gh and consequently generate an i nterrupt. c are m ust t herefore b e t aken i f sp urious wa ke-up si tuations a re t o b e a voided. i f a n interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interr upt enable bits have no ef fect on the interrupt wake-up function. rev. 1.10 154 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 155 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf3f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. rev. 1.10 154 ?an?a?? 1?? ?01? rev. 1.10 155 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom power down mode and wake-up entering the idle or sleep mode there is only one way for these devices to enter the sleep or idle mode and that is to execute the "halt" instructio n in the applicatio n program. when this instruction is executed, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock source and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present condition. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the devic e to as low a value as possible, perhaps only in the order of several micro-amps, there are other conside rations whic h m ust al so be ta ken int o ac count by the ci rcuit desi gner i f t he power consumption is to be minimised. special attention must be made to the i/o pins on these devices. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lirc oscillator. rev. 1.10 156 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 15? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if t he syst em i s woke n up by a n e xternal re set, t hese de vices wi ll e xperience a ful l syst em re set, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the "halt" instructio n. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an inte rrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately service d, but will rather be serviced later wh en t he r elated i nterrupt i s f inally e nabled o r wh en a st ack l evel b ecomes f ree. t he o ther situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. rev. 1.10 156 ?an?a?? 1?? ?01? rev. 1.10 15 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a l ow vo ltage c ondition wi ll be de termined. a l ow vo ltage c ondition i s i ndicated whe n t he l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo: lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 lvden: low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2~vlvd0: select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.4v rev. 1.10 158 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 159 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom lvd operation the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.4v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interru pt to be generated if v dd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. rev. 1.10 158 ?an?a?? 1?? ?01? rev. 1.10 159 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom scom function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the pc0~pc1, pc6~pc7 port. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the pc0~pc1, pc6~pc7 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/of f function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver , however this bit is used in conjunction with the comnen bits to select which port c pins are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation. lcd com bias scomen comnen pin function o/p level 0 x i/o 0 o ? 1 1 0 i/o 0 o ? 1 1 1 scomn v dd / ? output control rev. 1.10 160 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 161 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register ? ht66f30-1/HT68F30-1 bit 7 6 5 4 3 2 1 0 name d ? isel1 isel0 scomen com ? en com ? en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 isel1, isel0: select scom typical bias current (v dd =5v) 00: 25a 01: 50a 10: 100a 11: 200a bit 4 scomen: scom module control 0: disable 1: enable bit 3 com3en: pc7 or scom3 selection 0: gpio 1: scom3 bit 2 com2en: pc6 or scom2 selection 0: gpio 1: scom2 bit 1 com1en: pc1 or scom1 selection 0: gpio 1: scom1 bit 0 com0en: pc0 or scom0 selection 0: gpio 1: scom0 rev. 1.10 160 ?an?a?? 1?? ?01? rev. 1.10 161 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom confguration options confguration options refer to certain options within the mcu that are programmed into the devices during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the devices using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed s ? stem oscillato ? selection - f h : 1. hxt ? . erc ? . hirc ? low speed s ? stem oscillato ? selection - f l : 1. lxt ? . lirc ? wdt clock selection - f s : 1. f sub ? . f sys /4 4 hirc f ? eq ? enc ? selection: 1. 4mhz ? . 8mhz ? . 1 ? mhz note: the f sub and the f tbc clock so ?? ce a ? e lxt o ? lirc selection b ? the f l frq?xudwlrqrswlrq reset pin options 5 pb0/res pin options: 1. res pin ? . i/o pin watchdog options 6 watchdog time ? f ? nction: 1. enable ? . disable ? clr wdt inst ?? ctions selection: 1. 1 inst ?? ctions ? . ? inst ?? ctions lvr options 8 lvr f ? nction: 1. enable ? . disable 9 lvr voltage selection: 1. ? .10v ? . ? .55v ? . ? .15v 4. 4. ? 0v rev. 1.10 16 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 16? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom no. options sim options 10 sim f ? nction: 1. enable ? . disable 11 spi - wcol bit: 1. enable ? . disable 1 ? spi - csen bit: 1. enable ? . disable 1 ? i ? c debo ? nce time selection: 1. no debo ? nce ? . ? s ? stem clock debo ? nce ? . 4 s ? stem clock debo ? nce rev. 1.10 16? ?an?a?? 1?? ?01? rev. 1.10 16 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom application circuits ht66f30-1 note: "*": it is recommended that this component is added for added esd protection. "**": it is recommended that this component is added in environments where power line noise is signifcant. rev. 1.10 164 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 165 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom HT68F30-1 note: "*": it is recommended that this component is added for added esd protection. "**": it is recommended that this component is added in environments where power line noise is signifcant. rev. 1.10 164 ?an?a?? 1?? ?01? rev. 1.10 165 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. rev. 1.10 166 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 16? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been c arried out. t his i s done by pl acing a re turn i nstruction ret i n t he subrout ine whi ch wi ll cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.10 166 ?an?a?? 1?? ?01? rev. 1.10 16 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data memo ?? to acc 1 z ? c ? ac ? ov addm a ? [m] add acc to data memo ?? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data memo ?? to acc with ca ??? 1 z ? c ? ac ? ov adcm a ? [m] add acc to data memo ?? with ca ??? 1 note z ? c ? ac ? ov sub a ? x s ? bt ? act immediate data f ? om the acc 1 z ? c ? ac ? ov sub a ? [m] s ? bt ? act data memo ?? f ? om acc 1 z ? c ? ac ? ov subm a ? [m] s ? bt ? act data memo ?? f ? om acc with ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov sbc a ? [m] s ? bt ? act data memo ?? f ? om acc with ca ??? 1 z ? c ? ac ? ov sbcm a ? [m] s ? bt ? act data memo ?? f ? om acc with ca ???? ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov daa [m] decimal adj ? st acc fo ? addition with ? es ? lt in data memo ?? 1 note c logic operation and a ? [m] logical and data memo ?? to acc 1 z or a ? [m] logical or data memo ?? to acc 1 z xor a ? [m] logical xor data memo ?? to acc 1 z andm a ? [m] logical and acc to data memo ?? 1 note z orm a ? [m] logical or acc to data memo ?? 1 note z xorm a ? [m] logical xor acc to data memo ?? 1 note z and a ? x logical and immediate data to acc 1 z or a ? x logical or immediate data to acc 1 z xor a ? x logical xor immediate data to acc 1 z cpl [m] complement data memo ?? 1 note z cpla [m] complement data memo ?? with ? es ? lt in acc 1 z increment & decrement inca [m] inc ? ement data memo ?? with ? es ? lt in acc 1 z inc [m] inc ? ement data memo ?? 1 note z deca [m] dec ? ement data memo ?? with ? es ? lt in acc 1 z dec [m] dec ? ement data memo ?? 1 note z rotate rra [m] rotate data memo ?? ? ight with ? es ? lt in acc 1 none rr [m] rotate data memo ?? ? ight 1 note none rrca [m] rotate data memo ?? ? ight th ? o ? gh ca ??? with ? es ? lt in acc 1 c rrc [m] rotate data memo ?? ? ight th ? o ? gh ca ??? 1 note c rla [m] rotate data memo ?? left with ? es ? lt in acc 1 none rl [m] rotate data memo ?? left 1 note none rlca [m] rotate data memo ?? left th ? o ? gh ca ??? with ? es ? lt in acc 1 c rlc [m] rotate data memo ?? left th ? o ? gh ca ??? 1 note c rev. 1.10 168 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 169 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom mnemonic description cycles flag affected data move mov a ? [m] move data memo ?? to acc 1 none mov [m] ? a move acc to data memo ?? 1 note none mov a ? x move immediate data to acc 1 none bit operation clr [m].i clea ? bit of data memo ?? 1 note none set [m].i set bit of data memo ?? 1 note none branch ? mp add ? ?? mp ? nconditionall ? ? none sz [m] skip if data memo ?? is ze ? o 1 note none sza [m] skip if data memo ?? is ze ? o with data movement to acc 1 note none sz [m].i skip if bit i of data memo ?? is ze ? o 1 note none snz [m].i skip if bit i of data memo ?? is not ze ? o 1 note none siz [m] skip if inc ? ement data memo ?? is ze ? o 1 note none sdz [m] skip if dec ? ement data memo ?? is ze ? o 1 note none siza [m] skip if inc ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none sdza [m] skip if dec ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none call add ? s ? b ? o ? tine call ? none ret ret ?? n f ? om s ? b ? o ? tine ? none ret a ? x ret ?? n f ? om s ? b ? o ? tine and load immediate data to acc ? none reti ret ?? n f ? om inte ??? pt ? none table read tabrdc [m] read table to tblh and data memo ?? ? note none tabrdl [m] read table (last page) to tblh and data memo ?? ? note none miscellaneous nop no ope ? ation 1 none clr [m] clea ? data memo ?? 1 note none set [m] set data memo ?? 1 note none clr wdt clea ? watchdog time ? 1 to ? pdf clr wdt1 p ? e-clea ? watchdog time ? 1 to ? pdf clr wdt ? p ? e-clea ? watchdog time ? 1 to ? pdf swap [m] swap nibbles of data memo ?? 1 note none swapa [m] swap nibbles of data memo ?? with ? es ? lt in acc 1 none halt ente ? powe ? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf flags may be af fected by the execution st atus. t he t o a nd pdf fl ags a re c leared a fter bot h clr w dt1 a nd clr w dt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged. rev. 1.10 168 ?an?a?? 1?? ?01? rev. 1.10 169 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z rev. 1.10 1 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?1 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z rev. 1.10 1?0 ?an?a?? 1?? ?01? rev. 1.10 1 ? 1 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none rev. 1.10 1?? ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rev. 1.10 1 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?5 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none rev. 1.10 1?4 ?an?a?? 1?? ?01? rev. 1.10 1 ? 5 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c rev. 1.10 1 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none rev. 1.10 1?6 ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z rev. 1.10 1 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?9 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin dip (300mil) outline dimensions fig1. full lead packages fig1. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 0. ? 80 0.880 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.0 ? 0 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a 19.81 ?? . ? 5 b 6.10 ? .11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 f 1.14 1. ? 8 g ? .54 h ? .6 ? 8. ? 6 i 10.9 ? rev. 1.10 1?8 ?an?a?? 1?? ?01? rev. 1.10 1 ? 9 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ms-001d (see fg2) symbol dimensions in inch min. nom. max. a 0. ?? 5 D 0. ?? 5 b 0. ? 40 D 0. ? 80 c 0.115 D 0.195 d 0.115 D 0.150 e 0.014 D 0.0 ?? f 0.045 D 0.0 ? 0 g D 0.100 D h 0. ? 00 D 0. ?? 5 i D 0.4 ? 0 D symbol dimensions in mm min. nom. max. a 18.6 ? D 19.69 b 6.10 D ? .11 c ? .9 ? D 4.95 d ? .9 ? D ? .81 e 0. ? 6 D 0.56 f 1.14 D 1. ? 8 g D ? .54 D h ? .6 ? D 8. ? 6 i D 10.9 ? D rev. 1.10 180 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 181 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 0. ? 45 D 0. ? 85 b 0. ?? 5 D 0. ? 95 c 0.1 ? 0 D 0.150 d 0.110 D 0.150 e 0.014 D 0.0 ?? f 0.045 D 0.060 g D 0.100 D h 0. ? 00 D 0. ?? 5 i D 0.4 ? 0 D symbol dimensions in mm min. nom. max. a 18.9 ? D 19.94 b 6.99 D ? .49 c ? .05 D ? .81 d ? . ? 9 D ? .81 e 0. ? 6 D 0.56 f 1.14 D 1.5 ? g D ? .54 D h ? .6 ? D 8. ? 6 i D 10.9 ? D rev. 1.10 180 ?an?a?? 1?? ?01? rev. 1.10 181 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.15 ? c 0.01 ? D 0.0 ? 0 c ? 0. ? 86 D 0.40 ? d D D 0.069 e D 0.050 D f 0.004 D 0.010 g 0.016 D 0.050 h 0.00 ? D 0.010 0? D 8? symbol dimensions in mm min. nom. max. a 5. ? 9 D 6. ? 0 b ? .81 D ? .99 c 0. ? 0 D 0.51 c ? 9.80 D 10. ? 1 d D D 1. ? 5 e D 1. ?? D f 0.10 D 0. ? 5 g 0.41 D 1. ?? h 0.18 D 0. ? 5 0? D 8? rev. 1.10 18 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 18? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 16-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.15 ? c 0.008 D 0.01 ? c ? 0.189 D 0.19 ? d 0.054 D 0.060 e D 0.0 ? 5 D f 0.004 D 0.010 g 0.0 ?? D 0.0 ? 8 h 0.00 ? D 0.010 0? D 8? symbol dimensions in mm min. nom. max. a 5. ? 9 D 6. ? 0 b ? .81 D ? .99 c 0. ? 0 D 0. ? 0 c ? 4.80 D 5.00 d 1. ?? D 1.5 ? e D 0.64 D f 0.10 D 0. ? 5 g 0.56 D 0. ? 1 h 0.18 D 0. ? 5 0? D 8? rev. 1.10 18? ?an?a?? 1?? ?01? rev. 1.10 18 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 20-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 0.980 1.060 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.0 ? 0 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 4.89 ? 6.9 ? b 6.10 ? .11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 f 1.14 1. ? 8 g ? .54 h ? .6 ? 8. ? 6 i 10.9 ? rev. 1.10 184 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 185 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 0.945 D 0.985 b 0. ?? 5 D 0. ? 95 c 0.1 ? 0 D 0.150 d 0.110 D 0.150 e 0.014 D 0.0 ?? f 0.045 D 0.060 g D 0.100 D h 0. ? 00 D 0. ?? 5 i D 0.4 ? 0 D symbol dimensions in mm min. nom. max. a ? 4.00 D ? 5.0 ? b 6.99 D ? .49 c ? .05 D ? .81 d ? . ? 9 D ? .81 e 0. ? 6 D 0.56 f 1.14 D 1.5 ? g D ? .54 D h ? .6 ? D 8. ? 6 i D 10.9 ? D rev. 1.10 184 ?an?a?? 1?? ?01? rev. 1.10 185 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0. ? 9 ? D 0.419 b 0. ? 56 D 0. ? 00 c 0.01 ? D 0.0 ? 0 c ? 0.496 D 0.51 ? d D D 0.104 e D 0.050 D f 0.004 D 0.01 ? g 0.016 D 0.050 h 0.008 D 0.01 ? 0? D 8? symbol dimensions in mm min. nom. max. a 9.98 D 10.64 b 6.50 D ? .6 ? c 0. ? 0 D 0.51 c ? 1 ? .60 D 1 ? .00 d D D ? .64 e D 1. ?? D f 0.10 D 0. ? 0 g 0.41 D 1. ?? h 0. ? 0 D 0. ?? 0? D 8? rev. 1.10 186 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 18? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.158 c 0.008 D 0.01 ? c ? 0. ?? 5 D 0. ? 4 ? d 0.049 D 0.065 e D 0.0 ? 5 D f 0.004 D 0.010 g 0.015 D 0.050 h 0.00 ? D 0.010 0? D 8? symbol dimensions in mm min. nom. max. a 5. ? 9 D 6. ? 0 b ? .81 D 4.01 c 0. ? 0 D 0. ? 0 c ? 8.51 D 8.81 d 1. ? 4 D 1.65 e D 0.64 D f 0.10 D 0. ? 5 g 0. ? 8 D 1. ?? h 0.18 D 0. ? 5 0? D 8? rev. 1.10 186 ?an?a?? 1?? ?01? rev. 1.10 18 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 24-pin skdip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 1. ?? 0 1. ? 80 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.0 ? 0 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 1. ? 4 ?? .51 b 6.10 ? .11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 f 1.14 1. ? 8 g ? .54 h ? .6 ? 8. ? 6 i 10.9 ? rev. 1.10 188 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 189 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ms-001d (see fg2) symbol dimensions in inch min. nom. max. a 1.160 1.195 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.0 ? 0 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 9.46 ? 0. ? 5 b 6.10 ? .11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 f 1.14 1. ? 8 g ? .54 h ? .6 ? 8. ? 6 i 10.9 ? rev. 1.10 188 ?an?a?? 1?? ?01? rev. 1.10 189 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 1.145 1.185 b 0. ?? 5 0. ? 95 c 0.1 ? 0 0.150 d 0.110 0.150 e 0.014 0.0 ?? f 0.045 0.060 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 9.08 ? 0.10 b 6.99 ? .49 c ? .05 ? .81 d ? . ? 9 ? .81 e 0. ? 6 0.56 f 1.14 1.5 ? g ? .54 h ? .6 ? 8. ? 6 i 10.9 ? rev. 1.10 190 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 191 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 24-pin sop (300mil) outline dimensions ms-01 3 symbol dimensions in inch min. nom. max. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c 0.598 0.61 ? d 0.104 e 0.050 f 0.004 0.01 ? g 0.016 0.050 h 0.008 0.01 ? 0? 8? symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 ? .6 ? c 0. ? 0 0.51 c 15.19 15.5 ? d ? .64 e 1. ?? f 0.10 0. ? 0 g 0.41 1. ?? h 0. ? 0 0. ?? 0? 8? rev. 1.10 190 ?an?a?? 1?? ?01? rev. 1.10 191 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 24-pin ssop(150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.15 ? c 0.008 0.01 ? c 0. ?? 5 0. ? 46 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.00 ? 0.010 0? 8? symbol dimensions in mm min. nom. max. a 5. ? 9 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 8.51 8. ? 9 d 1. ?? 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0. ? 1 h 0.18 0. ? 5 0? 8? rev. 1.10 19 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 19? ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom reel dimensions 16-pin nsop(150mil), ssop 20s (150mil), ssop 24s (150mil) symbol description dimensions in mm a reel o ? te ? diamete ? ?? 0.01.0 b reel inne ? diamete ? 100.01.5 c spindle hole diamete ? 1 ? .0 +0.5/-0. ? d ke ? slit width ? .00.5 t1 space between flang 16.8 +0. ? /-0. ? t ? reel thickness ?? . ? 0. ? 16-pin ssop(150mil) symbol description dimensions in mm a reel o ? te ? diamete ? ?? 0.01.0 b reel inne ? diamete ? 100.01.5 c spindle hole diamete ? 1 ? .0 +0.5/-0. ? d ke ? slit width ? .00.5 t1 space between flang 1 ? .8 +0. ? /-0. ? t ? reel thickness 18. ? 0. ? sop 20w (300mil), sop 24w (300mil) symbol description dimensions in mm a reel o ? te ? diamete ? ?? 0.01.0 b reel inne ? diamete ? 100.01.5 c spindle hole diamete ? 1 ? .0 +0.5/-0. ? d ke ? slit width ? .00.5 t1 space between flang ? 4.8 +0. ? /-0. ? t ? reel thickness ? 0. ? 0. ? rev. 1.10 19? ?an?a?? 1?? ?01? rev. 1.10 19 ? ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom carrier tape dimensions 16-pin nsop (150mil) symbol description dimensions in mm w ca ?? ie ? tape width 16.00. ? p cavit ? pitch 8.00.1 e pe ? fo ? ation position 1. ? 50.1 f cavit ? to pe ? fo ? ation(width di ? ection) ? .50.1 d pe ? fo ? ation diamete ? 1.55 +0.10/-0.00 d1 cavit ? hole diamete ? 1.50 +0. ? 5/-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavit ? to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavit ? length 6.50.1 b0 cavit ? width 10. ? 0.1 k0 cavit ? depth ? .10.1 t ca ?? ie ? tape thickness 0. ? 00.05 c cove ? tape width 1 ? . ? 0.1 rev. 1.10 194 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 195 ?an?a?? 1?? ?01? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom 16-pin ssop (150mil) symbol description dimensions in mm w ca ?? ie ? tape width 1 ? .0 +0. ? /-0.1 p cavit ? pitch 8.00.1 e pe ? fo ? ation position 1. ? 50.10 f cavit ? to pe ? fo ? ation(width di ? ection) 5.50.1 d pe ? fo ? ation diamete ? 1.550.10 d1 cavit ? hole diamete ? 1.50 +0. ? 5/-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavit ? to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavit ? length 6.40.1 b0 cavit ? width 5. ? 0.1 k0 cavit ? depth ? .10.1 t ca ?? ie ? tape thickness 0. ? 00.05 c cove ? tape width 9. ? 0.1 sop 20w (300mil) symbol description dimensions in mm w ca ?? ie ? tape width ? 4.0 +0. ? /-0.1 p cavit ? pitch 1 ? .00.1 e pe ? fo ? ation position 1. ? 50.10 f cavit ? to pe ? fo ? ation(width di ? ection) 11.50.1 d pe ? fo ? ation diamete ? 1.5 +0.1/-0.0 d1 cavit ? hole diamete ? 1.50 +0. ? 5/-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavit ? to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavit ? length 10.80.1 b0 cavit ? width 1 ? . ? 0.1 k0 cavit ? depth ? . ? 0.1 t ca ?? ie ? tape thickness 0. ? 00.05 c cove ? tape width ? 1. ? 0.1 ssop 20s (150mil) symbol description dimensions in mm w ca ?? ie ? tape width 16.0 +0. ? /-0.1 p cavit ? pitch 8.00.1 e pe ? fo ? ation position 1. ? 50.10 f cavit ? to pe ? fo ? ation(width di ? ection) ? .50.1 d pe ? fo ? ation diamete ? 1.5 +0.1/-0.0 d1 cavit ? hole diamete ? 1.50 +0. ? 5/-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavit ? to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavit ? length 6.50.1 b0 cavit ? width 9.00.1 k0 cavit ? depth ? . ? 0.1 t ca ?? ie ? tape thickness 0. ? 00.05 c cove ? tape width 1 ? . ? 0.1 rev. 1.10 194 ?an?a?? 1?? ?01? rev. 1.10 195 ? an ? a ?? 1 ?? ? 01 ? ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom sop 24w symbol description dimensions in mm w ca ?? ie ? tape width 24.0 0.3 p cavit ? pitch 12.0 0.1 e pe ? fo ? ation position 1.75 0.10 f cavit ? to pe ? fo ? ation (width di ? ection) 11 .5 0.1 d pe ? fo ? ation diamete ? 1.55 +0.10/-0.00 d1 cavit ? hole diamete ? 1.50 +0.25/-0.00 p0 pe ? fo ? ation pitch 4.0 0.1 p1 cavit ? to pe ? fo ? ation (length di ? ection) 2.0 0.1 a0 cavit ? length 10.9 0.1 b0 cavit ? width 15.9 0.1 k0 cavit ? depth 3.1 0.1 t ca ?? ie ? tape thickness 0.35 0.05 c cove ? tape width 21.3 0.1 ssop 24s(150mil) symbol description dimensions in mm w ca ?? ie ? tape width 16.0 +0.3/-0.1 p cavit ? pitch 8.0 0.1 e pe ? fo ? ation position 1.75 0.10 f cavit ? to pe ? fo ? ation (width di ? ection) 7.5 0.1 d pe ? fo ? ation diamete ? 1.5 +0.1/-0.0 d1 cavit ? hole diamete ? 1.50 +0.25/-0.00 p0 pe ? fo ? ation pitch 4.0 0.1 p1 cavit ? to pe ? fo ? ation (length di ? ection) 2.0 0.1 a0 cavit ? length 6.5 0.1 b0 cavit ? width 9.5 0.1 k0 cavit ? depth 2.1 0.1 t ca ?? ie ? tape thickness 0.30 0.05 c cove ? tape width 13.3 0.1 rev. 1.10 196 january 17, 2013 rev. 1.10 pb january 17, 2013 ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom ht66f30-1/HT68F30-1 enhanced flash type 8-bit mcu with eeprom holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor (china) inc. (dongguan sales offce) building no.10, xinzhu court, (no.1 headquarters), 4 cuizhu road, songshan lake, dongguan, china 523808 tel: 86-769-2626-1300 fax: 86-769-2626-1311, 86-769-2626-1322 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880b fax: 1-510-252-9885 http://www.holtek.com copyright ? 2013 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw . |
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